s908ey8ad4cfjer Freescale Semiconductor, Inc, s908ey8ad4cfjer Datasheet - Page 46

• Manufacturer Part Number: s908ey8ad4cfjer
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Analog-to-Digital Converter (ADC) Module
3.3.3 Conversion Time
Conversion starts after a write to the ADSCR. A conversion is between 16 and 17 ADC clock cycles,
therefore:
The ADC conversion time is determined by the clock source chosen and the divide ratio selected. The
clock source is either the bus clock or CGMXCLK and is selectable by ADICLK located in the ADC clock
register. For example, if CGMXCLK is 4 MHz and is selected as the ADC input clock source, the ADC
input clock divide-by-2 prescale is selected and the bus frequency is 8 MHz:
Since an ADC cycle may be comprised of several bus cycles (four in the previous example) and the start
of a conversion is initiated by a bus cycle write to the ADSCR, from zero to four additional bus cycles may
occur before the start of the initial ADC cycle. This results in a fractional ADC cycle and is represented as
the 17th cycle.
3.3.4 Continuous Conversion
In continuous conversion mode, the ADC data registers ADRH and ADRL will be filled with new data after
each conversion. Data from the previous conversion will be overwritten whether that data has been read
or not. Conversions will continue until the ADCO bit is cleared. The COCO bit is set after the first
conversion and will stay set for the next several conversions until the next write of the ADC status and
control register or the next read of the ADC data register.
3.3.5 Result Justification
The conversion result may be formatted in four different ways:
All four of these modes are controlled using MODE0 and MODE1 bits located in the ADC clock register
(ADCLK).
Left justification will place the eight most significant bits (MSB) in the corresponding ADC data register
high, ADRH. This may be useful if the result is to be treated as an 8-bit result where the two least
significant bits (LSB), located in the ADC data register low, ADRL, can be ignored. However, ADRL must
be read after ADRH or else the interlocking will prevent all new conversions from being stored.
46
1. Left justified
2. Right justified
3. Left Justified sign data mode
4. 8-bit truncation mode
Number of bus cycles = (8 to 8.5µs) x 8 MHz = 64 to 68 cycles
Number of Bus Cycles = Conversion Time x Bus Frequency
Conversion time =
Conversion Time =
The ADC frequency must be between f
to meet A/D specifications. See
Characteristics.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
16 to17 ADC Cycles
16 to17 ADC Cycles
ADC Frequency
4 MHz/2
20.10 Analog-to-Digital Converter (ADC)
ADIC
= 8 to 8.5 µs
minimum and f
ADIC
maximum
Freescale Semiconductor