mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 13

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

READs
as shown in Figure 5.
vided with the READ command and AUTO
PRECHARGE is either enabled or disabled for that burst
access. If AUTO PRECHARGE is enabled, the row being
accessed is precharged at the completion of the burst.
For the generic READ commands used in the following
illustrations, AUTO PRECHARGE is disabled.
from the starting column address will be available
following the CAS latency after the READ command.
Each subsequent data-out element will be valid by the
next positive clock edge. Figure 6 shows general timing
for each possible CAS latency setting.
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
A0-A7
A8-A9
READ bursts are initiated with a READ command,
The starting column and bank addresses are pro-
During READ bursts, the valid data-out element
CAS#
RAS#
WE#
A10
CKE
CLK
CS#
BA
HIGH
READ Command
Figure 5
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
BANK 0
ADDRESS
COLUMN
BANK 1
13
commands have been initiated, the DQs will go High-
Z. A full-page burst will continue until terminated (at
the end of the page it will wrap to column 0 and
continue).
a subsequent READ command, and data from a fixed-
length READ burst may be immediately followed by
data from a subsequent READ command. In either
case, a continuous flow of data can be maintained. The
first data element from the new burst follows either the
last element of a completed burst, or the last desired
data element of a longer burst which is being trun-
cated. The new READ command should be issued x
cycles before the clock edge at which the last desired
COMMAND
COMMAND
COMMAND
Upon completion of a burst, assuming no other
Data from any READ burst may be truncated with
CLK
CLK
CLK
DQ
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
READ
READ
READ
T0
T0
T0
CAS Latency = 1
t
t AC
LZ
CAS Latency = 2
CAS Latency
Figure 6
NOP
NOP
T1
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
D
t OH
OUT
T2
NOP
T2
NOP
T2
t
t AC
LZ
D
t OH
OUT
16Mb: x16
IT SDRAM
©1999, Micron Technology, Inc.
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4