mt48lc1m16a1 Micron Semiconductor Products, mt48lc1m16a1 Datasheet - Page 14

• Manufacturer Part Number: mt48lc1m16a1
• Description: Synchronous Dram
• Manufacturer: Micron Semiconductor Products

data element is valid, where x equals the CAS latency
minus one. This is shown in Figure 7 for READ latencies
of one, two and three; data element n + 3 is either the
last of a burst of four or the last desired of a longer
burst. The 1 Meg x 16 SDRAM uses a pipelined architec-
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
COMMAND
COMMAND
COMMAND
ADDRESS
ADDRESS
ADDRESS
NOTE: Each READ command may be to either bank. DQM is LOW.
CLK
CLK
CLK
DQ
DQ
DQ
CAS Latency = 1
BANK,
T0
T0
T0
COL n
BANK,
BANK,
COL n
COL n
READ
READ
READ
CAS Latency = 2
CAS Latency = 3
Consecutive READ Bursts
T1
T1
T1
NOP
NOP
NOP
D
OUT
n
T2
T2
T2
NOP
NOP
NOP
D
D
n + 1
OUT
OUT
n
Figure 7
T3
T3
T3
14
NOP
NOP
NOP
D
D
n + 2
D
n + 1
OUT
OUT
OUT
n
ture and therefore does not require the 2n rule associ-
ated with a prefetch architecture. A READ command
can be initiated on any clock cycle following a previous
READ command. Full-speed, random read accesses
within a page can be performed as shown in Figure 8.
T4
T4
T4
BANK,
BANK,
READ
BANK,
READ
COL b
READ
COL b
COL b
X = 0 cycles
X = 1 cycle
D
D
n + 2
D
n + 1
n + 3
OUT
OUT
OUT
X = 2 cycles
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T5
T5
T5
NOP
NOP
NOP
D
D
n + 2
D
n + 3
OUT
OUT
OUT
b
T6
T6
NOP
NOP
D
D
n + 3
OUT
OUT
b
DON’T CARE
T7
NOP
D
OUT
b
16Mb: x16
IT SDRAM
©1999, Micron Technology, Inc.