mt46h32m32lfcm-6 Micron Semiconductor Products, mt46h32m32lfcm-6 Datasheet - Page 17

• Manufacturer Part Number: mt46h32m32lfcm-6
• Description: 1gb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Table 7:
PDF: 09005aef82ce3074/Source: 09005aef82cd0158
1gb_ddr_mobile_sdram_t48m_density__2.fm - Rev. G 07/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
Address inputs are switching every two clock cycles; Data bus
inputs are stable
Precharge power-down standby current: All banks idle; CKE is
LOW; CS is HIGH;
switching; Data bus inputs are stable
Precharge power-down standby current: Clock stopped; All banks
idle; CKE is LOW; CS is HIGH; CK = LOW, CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Precharge nonpower-down standby current: All banks idle;
CKE = HIGH; CS = HIGH;
are switching; Data bus inputs are stable
Precharge nonpower-down standby current: Clock stopped; All
banks idle; CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Address
and control inputs are switching; Data bus inputs are stable
Active power-down standby current: One bank active; CKE = LOW;
CS = HIGH;
switching; Data bus inputs are stable
Active power-down standby current: Clock stopped; One bank
active; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Active nonpower-down standby: One bank active; CKE = HIGH;
CS = HIGH;
switching; Data bus inputs are stable
Active nonpower-down standby: Clock stopped; One bank active;
CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Operating burst read: One bank active; BL = 4;
Continuous READ bursts; I
every two clock cycles; 50 percent data changing each burst
Operating burst write: One bank active; BL = 4;
Continuous WRITE bursts; Address inputs are switching; 50 percent
data changing each burst
Auto refresh: Burst refresh; CKE = HIGH;
Address and control inputs are switching; Data
bus inputs are stable
Deep power-down current: Address and control balls are stable;
Data bus inputs are stable
CK =
t
CK (MIN); CKE is HIGH; CS is HIGH between valid commands;
t
t
CK =
CK =
I
Notes: 1–5 apply to all the parameters/conditions in this table; notes appear on page 19;
V
DD
DD
t
t
/V
t
CK (MIN); Address and control inputs are
CK (MIN); Address and control inputs are
Specifications and Conditions (x16)
CK =
DD
Q = 1.70–1.95V
t
t
CK (MIN); Address and control inputs are
CK =
OUT
t
CK (MIN); Address and control inputs
= 0mA; Address inputs are switching
t
t
RC =
CK =
t
CK =
t
t
RFC = 138ns
RFC =
t
RC (MIN);
t
CK (MIN);
t
CK (MIN);
t
REFI
17
Symbol
I
I
I
I
I
I
I
I
DD
DD
I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
I
DD
I
DD
DD
DD
DD
DD
I
DD
DD
DD
I
I
DD
DD
DD
2NS
3NS
2PS
3PS
4W
2N
3N
5A
2P
3P
4R
0
5
8
1Gb: x16, x32 Mobile DDR SDRAM
130
130
140
80
18
14
20
14
15
-5
125
125
140
-54
75
17
13
19
14
15
Electrical Specifications
Max
600
600
3.6
3.6
10
115
115
140
©2007 Micron Technology, Inc. All rights reserved
70
15
18
14
15
-6
8
105
105
140
-75
60
12
16
12
14
8
Unit Notes
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
10, 11
7, 13
7, 8
10
6
7
9
9
8
6
6
6
6