ics9248-165 Integrated Device Technology, ics9248-165 Datasheet

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ics9248-165

Manufacturer Part Number
ics9248-165
Description
Frequency Generator & Integrated Buffers For Celeron & Pii/iii
Manufacturer
Integrated Device Technology
Datasheet
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Third party brands and names are the property of their respective owners.
Recommended Application:
440BX/VIA Apollo 133 style chipset.
Output Features:
Features:
Skew Specifications:
Block Diagram
CLK_STOP#
PCI_STOP#
BUFFER IN
9248-165 Rev A 4/20/01
FS(3:0)
SDATA
MODE
2 - CPUs @ 2.5V or 3.3V up to 166MHz.
1 - IOAPIC @ 2.5V or 3.3V
13 - SDRAM @ 3.3V
6 - PCI @ 3.3V,
1 - 48MHz, @ 3.3V fixed.
1 - 24MHz @ 3.3V
2 - REF @ 3.3V, 14.318MHz.
Up to 166MHz frequency support
Supports power management: PCI, CPU stop and Mode
Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
Uses external 14.318MHz crystal
CPU – CPU: <175ps
SDRAM - SDRAM: <500ps
PCI – PCI: <500ps
CPU-SDRAM: <500ps
CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
SCLK
X2
X1
4
XTAL
OSC
Spectrum
PLL2
POR
Spread
PLL1
Integrated
Circuit
Systems, Inc.
Config.
Control
LATCH
Reg.
Logic
4
/2
DIVDER
CLOCK
PCI
STOP
STOP
STOP
STOP
12
2
5
48MHz
24MHz
IOAPIC
CPUCLK_F
SDRAM (11:0)
SDRAM_F
PCICLK (4:0)
PCICLKF
CPUCLK 1
REF(1:0)
Functionality
*MODE/PCICLK_F
*PCI_STOP/REF0
**FS3/PCICLK0
F
0
0
0
0
0
0
0
0
S
1
1
1
1
1
1
1
1
3
BUFFER IN
SDRAM11
SDRAM10
PCICLK1
PCICLK2
PCICLK3
PCICLK4
SDRAM9
SDRAM8
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
* Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down resistor of 120K to GND
SDATA
VDD1
VDD2
VDD2
VDD3
SCLK
F
GND
GND
GND
GND
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X1
X2
2
48-Pin 300mil SSOP
Pin Configuration
F
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
1
2
3
4
5
6
7
8
9
F
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
ICS9248-165
(
0 1
0 1
2 1
1 1
0 1
0 1
4 1
5 1
2 1
3 1
1 1
6
8
6
8
7
C
M
. 6
. 0
. 5
. 3
. 8
. 3
. 0
. 0
. 4
. 9
. 5
. 0
. 0
. 4
. 3
P
. 2
H
0 0
0 0
2 8
1 0
1 3
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
U
0 0
0 0
9 9
0 0
0 0
0 0
0 0
0 9
1 0
3 2
9 9
) z
VDDL
IOAPIC
REF1/FS2*
GND
CPUCLK_F
CPUCLK1
VDDL
CLK_STOP#*
SDRAM_F
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD3
SDRAM6
SDRAM7
VDD4
48MHz/FS0*
24MHz/FS1*
P
(
C
4
3
4
3
4
3
3
3
3
3
3
M
3
3
3
3
3
. 0
. 0
C I
. 7
. 1
. 3
. 4
. 7
. 4
. 3
. 8
. 6
. 5
. 5
. 7
. 1
. 3
H
0 0
0 5
0 0
0 0
0 0
0 5
0 0
5 6
1 4
3 3
4 3
1 0
1 4
3 3
6 6
7 4
L
) z
K

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ics9248-165 Summary of contents

Page 1

... ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-165 48 1 VDDL ...

Page 2

... ICS9248-165 Pin Descriptions ...

Page 3

... General Description The ICS9248-165 is a single chip clock solution for Desktop designs. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-165 ...

Page 4

... ICS9248-165 General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends a dummy command code • ...

Page 5

... ± ICS9248-165 ...

Page 6

... ICS9248-165 Byte 1: CPU, Active/Inactive Register (1= enable disable ...

Page 7

... CLK_STOP asychronous input to the clock synthesizer used to turn off the CPU, IOAPIC, SDRAM clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-165. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU, IOAPIC, SDRAM clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...

Page 8

... ICS9248-165 PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-165 used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-165 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed ...

Page 9

... The programming resistors should be located close to the series termination resistor to minimize the current loop area more important to locate the series termination resistor close to the driver than the programming resistor. Via to VDD 2K 8.2K Clock trace to load Series Term. Res. Fig ICS9248-165 ...

Page 10

... ICS9248-165 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0 Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied ...

Page 11

... L CONDITIONS ICS9248-165 MIN TYP MAX UNITS 2 2.4 V 0.17 0.4 V -58 - 1.08 1.6 ns 0. 175 ps 216 250 ps MIN TYP MAX UNITS 2 ...

Page 12

... ICS9248-165 Electrical Characteristics - SDRAM 70C 3.3V +/-5 DDL PARAMETER SYMBOL Output High Voltage V OH3 Output Low Voltage V OL3 Output High Current I OH3 I Output Low Current OL3 1 Rise Time Fall Time Duty Cycle 1 Skew window t sk3 1 (Buffer In to ...

Page 13

... Third party brands and names are the property of their respective owners. = 2.5V +/-5 (unless otherwise stated) L CONDITIONS ICS9248-165 MIN TYP MAX UNITS 2.4 3.03 V 0.23 0.4 V -50 - 1.26 4.0 ns 1. ...

Page 14

... ICS9248-165 INDEX INDEX AREA AREA 45° 45° SEATING SEATING b PLANE PLANE .10 (.004) C .10 (.004) C 300 mil SSOP Package Ordering Information ICS9248yF-165-T Example: ICS XXXX PPP - T Designation for tape and reel packaging Pattern Number ( digit number for parts with ROM code patterns) ...

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