ics9248-185 Integrated Device Technology, ics9248-185 Datasheet
ics9248-185
Related parts for ics9248-185
ics9248-185 Summary of contents
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... ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-185 TM & ...
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... ICS9248-185 General Description The ICS9248-185 is the single chip clock solution for Notebook designs using the 440BX or the VIA Apollo Pro 133 style chipset. It provides all necessary clock signals for such a system. The ICS9248-185 provides CPU and PCI clocks with continous spread spectrum. The ICS9248-185 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations ...
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... Select @ 66MHz pF; Select @ 100MHz pF; Select @ 133MHz pF; Input address VDD or GND Logic Inputs X1 & X2 pins From target Freq 1 ICS9248-185 +0 MIN TYP MAX -0.3 0 150 67 170 73 180 600 12 14 ...
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... ICS9248-185 Electrical Characteristics - CPU 70C 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH2A Output Low Voltage V OL2A Output High Current I OH2A Output Low Current I OL2A 1 Rise Time t r2A 1 Fall Time t f2A 1 d Duty Cycle t2A 1 Skew window t sk2A 1 Jitter, Cycle-to-cycle ...
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... L CONDITIONS ICS9248-185 MIN TYP MAX UNITS 2 0.2 0.4 V - 500 ps 145 500 ps MIN TYP MAX UNITS 2 ...
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... ICS9248-185 Electrical Characteristics - REF 70C 3.3 V, VDDL= 2.5V +/-5 PARAMETER SYMBOL Output High Voltage V OH5 Output Low Voltage V OL5 Output High Current I OH5 Output Low Current I OL5 1 Rise Time Fall Time Duty Cycle Jitter, cycle to cycle t jcycle5 1 Guaranteed by design, not 100% tested in production ...
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... CLK_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-185. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
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... ICS9248-185 PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-185 used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-185 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed ...
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... The programming resistors should be located close to the series termination resistor to minimize the current loop area more important to locate the series termination resistor close to the driver than the programming resistor. Via to VDD 2K 8.2K Clock trace to load Series Term. Res. Fig ICS9248-185 ...
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... ICS9248-185 INDEX INDEX AREA AREA .10 (.004) C .10 (.004) C 209 mil SSOP Ordering Information ICS9248yF-185-T Example: ICS XXXX PPP - Designation for tape and reel packaging T Pattern Number ( digit number for parts with ROM code patterns) ...
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... ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to 11 obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-185 In Millimeters In Inches COMMON DIMENSIONS MIN ...