ics9248-195 Integrated Device Technology, ics9248-195 Datasheet

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ics9248-195

Manufacturer Part Number
ics9248-195
Description
Frequency Generator & Integrated Buffers For Pentium Ii/iii & K6
Manufacturer
Integrated Device Technology
Datasheet
Frequency Generator & Integrated Buffers for PENTIUM II/III
Block Diagram
0375D—02/02/04
Recommended Application:
440BX, MX, VIA PM/PL/PLE 133 style chip set, with
Coppermine or Tualatin processor, for note book
applications.
Output Features:
Features:
including 1 free running CPUCLK_F
1 - PCI Early @ 3.3V
Up to 137MHz frequency support
97MHz to support high-end AMD processor.
Support power management: CLK, PCI, stop and
Power down Mode from I
Spread spectrum for EMI control
Uses external 14.318MHz crystal
FS pins for frequency select
7 - PCI @ 3.3V, including 1 free running PCICLK_F
4 - CPUs @ 2.5V/3.3V
9 - SDRAM @ 3.3V
1 - 48MHz, @ 3.3V fixed.
1 - 24/48MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
Integrated
Circuit
Systems, Inc.
2
C programming.
*CPU2.5_3.3#/PCICLK_F
*SELPCIE_6#/PCICLK2
*SEL24_48#/PCICLK1
Key Specifications:
PCICLK6/
Functionality
*Vtt_PWRGD/PD#
B
*SPREAD/REF0
0
0
0
0
0
0
0
0
i
1
1
1
1
1
1
1
1
*FS3/PCICLK0
2 t
CPU Output Jitter @ 2.5V: <300ps
CPU Output Jitter @ 3.3V: <250ps
PCI Output Jitter @ 3.3V: <250ps
CPU Output Skew @ 2.5V: <175ps
CPU Output Skew @ 3.3V: <175ps
PCI Output Skew @ 3.3V: <500ps
PCI Early to PCI Skew @ 3.3V: typ = 3ns
SDRAM Output Skew @ 3.3V: <500ps
PCI_STOP#
BUFFER IN
* Internal Pull-up Resistor of 120K to VDD
PCICLK_E
VDDCOR
GNDREF
VDDREF
PCICLK3
PCICLK4
PCICLK5
GNDPCI
GNDPCI
VDDPCI
VDDPCI
B
GND48
SDATA
SCLK
0
0
0
0
0
0
0
0
i
1
1
1
1
1
1
1
1
6 t
48-Pin SSOP and TSSOP
X1
X2
Pin Configuration
B
0
0
0
0
0
0
0
0
i
1
1
1
1
1
1
1
1
5 t
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
B
0
0
0
0
0
0
0
0
i
1
1
1
1
1
1
1
1
4 t
C
P
1
1
1
1
1
1
1
1
1
1
6
6
6
6
9
7
ICS9248-195
0
3
0
0
3
0
3
0
3
4
U
6
6
6
6
0
0
0
3
0
0
3
0
3
5
3
0
6 .
6 .
6 .
6 .
0 .
0 .
C
0 .
3 .
0 .
0 .
3 .
0 .
3 .
0 .
3 .
0 .
7
7
7
7
0
0
L
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
0
3
0
0
3
0
3
0
3
0
K
P
TM
REF1/FS2*
VDDLCPU
CPUCLK_F
CPUCLK0
GNDLCPU
CPUCLK1
CPUCLK2
CLK_STOP#
GNDSDR
SDRAM_F
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GNDSDR
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24_48MHz/FS1*
C
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
0
3
5
5
3
5
I
C
3 .
3 .
3 .
3 .
3 .
3 .
3 .
3 .
3 .
3 .
0 .
3 .
0 .
0 .
3 .
0 .
L
& K6
3
3
3
3
3
3
3
3
3
3
0
3
0
0
3
0
K

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ics9248-195 Summary of contents

Page 1

... ICS9248-195 TM & REF1/FS2* 47 VDDLCPU 46 CPUCLK_F 45 CPUCLK0 44 GNDLCPU 43 CPUCLK1 42 CPUCLK2 41 CLK_STOP# 40 GNDSDR 39 SDRAM_F 38 SDRAM0 37 SDRAM1 36 VDDSDR 35 SDRAM2 34 SDRAM3 33 GNDSDR 32 SDRAM4 31 SDRAM5 30 ...

Page 2

... ICS9248-195 Pin Descriptions ...

Page 3

... General Description The ICS9248-195 is the single chip clock solution for Notebook designs using the 440BX, MX, VIA PM/PL/PLE 133 style chip set, with Coppermine or Tualatin processor, for Note book applications. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I to 10dB ...

Page 4

... ICS9248-195 Byte 1: Active/Inactive Register (1 = enable disable ...

Page 5

... ICS9248-195 ...

Page 6

... ICS9248-195 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0 Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Case Temperature . . . . . . . . . . . . . . . . . . . . . 115°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied ...

Page 7

... 1.25 V, < 133 MHz 1.25 V, >= 133 MHz 1. 1. ICS9248-195 MIN TYP MAX UNITS 2.4 V 0 175 ps 160 250 ps MIN TYP MAX UNITS 2 V ...

Page 8

... ICS9248-195 Electrical Characteristics - PCI 70° 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH1 Output Low Voltage V OL1 Output High Current I OH1 Output Low Current I OL1 1 Rise Time Fall Time Duty Cycle Skew window t sk1 1 Skew window ...

Page 9

... (unless otherwise stated) L CONDITIONS ICS9248-195 MIN TYP MAX UNITS 2.4 V 0 436 600 ps MIN TYP MAX UNITS 2.4 2.6 V 0.22 0.4 V -32 ...

Page 10

... ICS9248-195 General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends a dummy command code • ...

Page 11

... The programming resistors should be located close to the series termination resistor to minimize the current loop area more important to locate the series termination resistor close to the driver than the programming resistor. Via to VDD 2K 8.2K Clock trace to load Series Term. Res. Fig ICS9248-195 ...

Page 12

... ICS9248-195 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. ...

Page 13

... CLK_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-195. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...

Page 14

... ICS9248-195 PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-195 used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-195 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed ...

Page 15

... Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 15 ICS9248-195 In Millimeters In Inches COMMON DIMENSIONS MAX MIN 2.80 .095 0.40 .008 0.34 ...

Page 16

... ICS9248-195 INDEX INDEX AREA AREA aaa (0.020 mil) (240 mil) 6.10 mm. Body, 0.50 mm. pitch TSSOP Ordering Information ICS9248yG-195LF-T Example: ICS XXXX y G LF- T 0375D—02/02/04 c SYMBOL aaa VARIATIONS - SEATING SEATING ...

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