ics9248-99 Integrated Device Technology, ics9248-99 Datasheet
ics9248-99
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ics9248-99 Summary of contents
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... ICS9248-99 Pin Configuration 48-Pin 300mil SSOP ...
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... ICS9248-99 General Description The ICS9248-99 is the single chip clock solution for Desktop designs using 810/810/E style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding ...
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... ACK ACK ACK ACK ACK 2 C component. It can read back the data stored in the latches for 2 C interface, the protocol is set to use only "Block-Writes" from the controller. The 3 ICS9248- programming. How to Read: ICS (Slave/Receiver) Start Bit Address D3 (H) ACK Byte Count ...
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... ICS9248-99 Serial Configuration Command Bitmap Byte4: Functionality and Frequency Select Register (default = ...
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... Note: Don’t write into this register, writing into this register can cause malfunction 5 ICS9248- ...
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... ICS9248-99 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS9248- 99 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of ...
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... Fig. 2a Fig ICS9248-99 ...
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... REF clock outputs in the LOW state may require more than one clock cycle to complete. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-99 device shown, the outputs Stop Low on the next falling edge after PD# goes low. ...
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... crossing of target Freq. trans st From 1 crossing to 1% target T s Freq. From target DD T STAB Freq. ,t output enable delay (all outputs) PZH ,t output disable delay(all outputs) PZH 9 ICS9248-99 +0 MIN TYP MAX 0 0.8 0 -200 -100 60 100 ...
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... ICS9248-99 Electrical Characteristics - CPU 70C 2.5V +/-5 DDL PARAMETER SYMBOL Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter 1 Guaranteed by design, not 100% tested in production. ...
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... V @ MIN=1 OL3 V @ MAX 1.5 V sk3 1.5 V jcyc-cyc T 11 ICS9248-99 MIN TYP MAX 0.4 -36 - 2.0 V 0.4 0.9 1.6 = 0.4 V 0.4 1.5 1 120 500 MIN TYP MAX 2.4 0.4 -54 -46 ...
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... ICS9248-99 Electrical Characteristics - PCI 70C 3.3V +/-5 PARAMETER SYMBOL Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - REF1, 48MHz 70C ...
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... ° 0 ° 5 ° F=SSOP ICS Standard Device 13 ICS9248- ...