ics9248-96 Integrated Device Technology, ics9248-96 Datasheet

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ics9248-96

Manufacturer Part Number
ics9248-96
Description
Frequency Generator & Integrated Buffers For Celeron & Pii/iii?
Manufacturer
Integrated Device Technology
Datasheet
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E type chipset.
Output Features:
Features:
Skew Specifications:
Block Diagram
0311D—04/23/04
2- CPUs @ 2.5V, up to 166.5MHz.
9 - SDRAM @ 3.3V, up to 155MHz including
1 free running
8 - PCICLK @ 3.3V
1 - IOAPIC @ 2.5V,
2 - 3V66MHz @ 3.3V, 2X PCI MHz
2 - 48MHz, @ 3.3V fixed.
1 - 24/48MHz, @3.3V selectable by I
1 - REF @v3.3V, 14.318MHz.
Up to 166.5MHz frequency support
Support FS0-FS3 strapping status bit for I
back.
Support power management: Through Power down
Mode from I
Spread spectrum for EMI control ( ± 0.25% center).
Uses external 14.318MHz crystal
CPU – CPU: <175ps
SDRAM - SDRAM: < 250ps
3V66 – 3V66: <175ps
PCI – PCI: <500ps
CPU-SDRAM<500ps
For group skew specifications, please refer to group
timing relationship table.
2
Integrated
Circuit
Systems, Inc.
C programming.
2
C
2
C read
Functionality
Additional
programming.
F
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
3
F
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
F
0
0
0
0
0
0
0
0
S
1
1
1
1
1
1
1
1
** 60K pull-up to VDD on indicated input
1
* These inputs have a 120K pull up to VDD.
1 These are double strength.
frequencies
F
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
6
6
7
(
C
0
0
3
4
3
3
4
4
1
2
3
3
5
M
6
8
2
48-Pin 300mil SSOP
0
3
3
5
3
7
0
0
8
4
3
7
0
P
H
8 .
0 .
5 .
3 .
0 .
7 .
0 .
7 .
3 .
0 .
0 .
0 .
0 .
7 .
0 .
0 .
U
Pin Configuration
) z
0
0
0
0
0
3
0
3
3
0
0
0
0
0
0
0
S
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(
D
0
0
0
0
0
0
0
0
0
4
1
2
3
3
1
0
M
R
0
2
0
3
0
8
0
3
5
0
8
4
3
7
2
8
H
2 .
0 .
3 .
0 .
3 .
7 .
3 .
0 .
0 .
0 .
0 .
0 .
7 .
0 .
5 .
7 .
A
) z
selectable
M
0
0
0
0
0
5
0
0
0
0
0
0
0
0
0
5
(
6
6
6
6
6
7
6
6
7
9
7
8
8
9
7
7
3
M
6
8
6
8
6
2
6
8
0
3
8
2
9
1
5
2
V
H
8 .
0 .
8 .
6 .
8 .
5 .
8 .
6 .
0 .
3 .
6 .
6 .
1 .
3 .
0 .
5 .
6
) z
6
0
0
7
7
7
0
7
7
0
3
7
7
3
3
0
0
ICS9248-96
P
(
3
3
3
3
3
3
3
3
3
4
3
4
4
4
3
3
C
M
3
4
3
4
3
6
3
4
5
6
9
1
4
5
7
6
I
H
C
4 .
0 .
4 .
3 .
4 .
2 .
4 .
3 .
0 .
6 .
3 .
3 .
5 .
6 .
5 .
2 .
) z
L
through
0
0
3
3
3
5
3
3
0
7
3
3
7
7
0
5
K
1
=
I
2
2
2
2
O
P
(
1
1
1
1
1
1
1
1
1
1
1
1
M
C
3
0
2
2
6
7
6
7
6
8
6
7
7
9
8
8
A
I
H
3 .
6 .
2 .
8 .
7 .
0 .
7 .
1 .
7 .
1 .
7 .
1 .
5 .
6 .
7 .
1 .
C
I P
L
) z
0
0
7
3
7
0
3
7
7
8
3
5
3
2
2
2
C
K
2 /
I
2
0
I
=
3
3
3
3
3
3
3
3
3
4
3
4
4
4
3
3
C
O
(
P
M
3
4
3
4
3
6
3
4
5
6
9
1
4
5
7
6
A
C
H
4 .
0 .
4 .
3 .
4 .
2 .
4 .
3 .
0 .
6 .
3 .
3 .
5 .
6 .
5 .
2 .
I P
I
C
) z
0
0
3
3
3
5
3
3
0
7
3
3
7
7
0
5
L
C
K

Related parts for ics9248-96

ics9248-96 Summary of contents

Page 1

... Additional frequencies programming. ICS9248-96 Pin Configuration 48-Pin 300mil SSOP ...

Page 2

... ICS9248-96 General Description ICS9248-96 is the single chip clock solution for designs using the 810/810E style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding ...

Page 3

... ACK ACK ACK ACK ACK 2 C component. It can read back the data stored in the latches for 2 C interface, the protocol is set to use only "Block-Writes" from the controller. 3 ICS9248- programming. How to Read: ICS (Slave/Receiver) Start Bit Address D3 (H) ACK Byte Count ...

Page 4

... ICS9248-96 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = ...

Page 5

... Note: Don’t write into this register. Writing into this register can cause malfunction 5 ICS9248- ...

Page 6

... ICS9248-96 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS9248- 96 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of ...

Page 7

... As shown, the outputs Stop Low on the next falling edge after PD# goes low asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. 0311D—04/23/04 7 ICS9248-96 ...

Page 8

... ICS9248-96 Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0 Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied ...

Page 9

... 1 3.135 ICS9248-96 MIN TYP MAX UNITS 13 2.5 V 0.2 0.4 V -85 - 0.5 1 0.5 1 175 ps 200 250 ...

Page 10

... ICS9248-96 Electrical Characteristics - IOAPIC 70° 2.5 V +/-5 DDL PARAMETER SYMBOL 1 R Output Impedance DSP2B Output High Voltage V OH2B V Output Low Voltage OL2B I Output High Current OH I Output Low Current Rise Time Fall Time Duty Cycle t 1 Jitter, Cycle-to-cycle ...

Page 11

... 1 3.135 1.5 V; 48MHz 1.5 V; REF T 11 ICS9248-96 MIN TYP MAX UNITS 2.4 3.2 V 0.1 0.55 V -33 -136 mA -13 -33 30 115 0.5 1 0 330 500 ...

Page 12

... ICS9248- INDEX INDEX AREA AREA 45° 45° Ordering Information ICS9248yF-96LF-T Example: ICS XXXX y F LF- T 0311D—04/23/04 c SYMBOL VARIATIONS N 48 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 - SEATING ...

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