ics9248-112 Integrated Device Technology, ics9248-112 Datasheet

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ics9248-112

Manufacturer Part Number
ics9248-112
Description
Frequency Generator & Integrated Buffers For Celeron
Manufacturer
Integrated Device Technology
Datasheet
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E type chipset.
Output Features:
Features:
Skew Specifications:
Block Diagram
0326C—09/18/03
2- CPUs @2.5V, up to 166.5MHz.
9 - SDRAM @ 3.3V, up to150MHz including
1 free running
8 - PCICLK @ 3.3V
1 - IOAPIC @ 2.5V, PCI or PCI/2 MHz
2 - 3V66MHz @ 3.3V, 2X PCI MHz
1- 48MHz, @3.3V fixed.
1- 24MHz, @3.3V fixed
1- REF @3.3V, 14.318MHz.
Up to 166MHz frequency support
Support FS0-FS3 strapping status bit for I
back.
Support power management: Through Power down
Mode from I
Spread spectrum for EMI control ( ± 0.25% center).
Spread can be enabled or disabled to all 32
frequencies throuth I
Uses external 14.318MHz crystal
CPU – CPU: <175ps
SDRAM - SDRAM: < 250ps
3V66 – 3V66: <175ps
PCI – PCI: <500ps
CPU-SDRAM<500ps
For group skew specifications, please refer to group
timing relationship table.
2
Integrated
Circuit
Systems, Inc.
C programming.
2
C.
2
[1:0]
C read
Functionality
Additional
programming.
F
0
0
0
0
0
0
0
0
S
1
1
1
1
1
1
1
1
3
F
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
F
0
0
0
0
0
0
0
0
S
1
1
1
1
1
1
1
1
1
VDDREF
* These inputs have a 120K pull up to VDD.
1. These are double strength.
F
frequencies
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0 1
0 1
3 1
4 1
3 1
3 1
4 1
4 1
1 1
2 1
3 1
3 1
5 1
(
6
6
7
M
C
. 6
. 8
. 2
. 0
. 3
. 5
. 0
. 0
. 8
. 4
. 3
. 7
. 0
Pin Configuration
P
. 3
. 3
. 7
48-Pin 300mil SSOP
H
0 8
0 0
0 5
U
0 3
0 0
0 0
0 0
0 0
0 0
0 0
0 7
0 0
0 0
3 7
3 7
3 3
) z
S
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
4 1
1 1
2 1
3 1
3 1
1 1
0 1
0 1
(
D
M
R
. 0
. 2
. 0
. 3
. 0
. 8
. 0
. 3
. 5
. 0
. 8
. 4
. 3
. 7
. 2
. 8
H
A
0 2
0 0
0 3
0 0
0 3
5 7
0 3
0 0
0 0
0 0
0 0
0 0
0 7
0 0
0 5
5 7
) z
M
selectable
(
6
6
6
6
6
7
6
6
7
9
7
8
8
9
7
7
3
M
. 6
. 8
. 2
. 0
. 8
. 5
. 2
. 6
. 8
. 6
. 6
. 8
. 3
. 2
. 9
. 1
V
H
6
0 8
0 0
0 5
0 0
7 6
0 0
0 5
7 8
7 6
7 8
7 8
7 6
3 3
7 6
3 1
3 3
6
) z
ICS9248-112
P
(
3
3
3
4
4
4
3
C
3
3
3
3
3
3
3
4
3
M
. 3
. 4
. 3
. 4
. 3
. 6
. 3
. 4
. 5
. 6
. 9
. 1
. 4
. 5
. 7
. 6
I
C
H
0 4
0 0
3 4
3 3
3 4
5 2
3 4
3 3
0 0
7 6
3 3
3 3
7 5
7 6
0 5
5 2
L
) z
K
through
1
I
=
O
(
P
1
1
1
1
1
1
1
1
1
2
1
2
2
2
1
1
M
C
. 3
. 0
. 2
. 2
A
. 6
. 7
. 6
. 7
. 6
. 8
. 6
. 7
. 7
. 9
. 8
. 8
I
H
C
I P
3 3
7 6
8 2
3 8
0 7
0 0
2 7
7 1
2 7
3 1
2 7
7 1
0 5
7 6
5 7
3 1
L
) z
C
K
2 /
0
I
I
=
(
O
3
3
3
3
3
3
3
3
3
4
3
4
4
4
3
3
2
P
M
. 3
. 4
. 3
. 4
. 3
. 6
. 3
. 4
. 5
. 6
. 9
. 1
. 4
. 5
. 7
. 6
A
C
C
H
I
I P
0 4
0 0
3 4
3 3
3 4
5 2
3 4
3 3
0 0
7 6
3 3
3 3
7 5
7 6
0 5
5 2
C
) z
L
C
K

Related parts for ics9248-112

ics9248-112 Summary of contents

Page 1

... Additional frequencies programming. ICS9248-112 ...

Page 2

... ICS9248-112 General Description The ICS9248-112 is a single chip clock solution for designs using the 810/810E style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding ...

Page 3

... ACK ACK ACK ACK ACK 2 C component. It can read back the data stored in the latches for 2 C interface, the protocol is set to use only "Block-Writes" from the controller. 3 ICS9248-112 2 C programming. How to Read: ICS (Slave/Receiver) Start Bit Address D3 (H) ACK Byte Count ...

Page 4

... ICS9248-112 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = ...

Page 5

... Note: Don’t write into this register. Writing into this register can cause malfunction 5 ICS9248-112 ...

Page 6

... ICS9248-112 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS9248- 112 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of ...

Page 7

... As shown, the outputs Stop Low on the next falling edge after PD# goes low asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. 0326C—09/18/03 7 ICS9248-112 ...

Page 8

... ICS9248-112 Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0 Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied ...

Page 9

... 1 MIN V = 3.135 MAX MIN MAX ICS9248-112 MIN TYP MAX UNITS 13 2.5 V 0.015 0.4 V -85 - 0.4 1.1 1.6 ns 0.4 1.1 1 ...

Page 10

... ICS9248-112 Electrical Characteristics - IOAPIC 70C 2.5 V +/-5 DDL PARAMETER SYMBOL 1 Output Impedance R DSP4B 1 Output Impedance R DSN4B Output High Voltage V OH4B Output Low Voltage V OL4B Output High Current I OH4B Output Low Current I OL4B 1 Rise Time t r4B 1 t Fall Time f4B 1 d Duty Cycle ...

Page 11

... 1 MIN V = 3.135 MAX MIN MAX 1.5 V; 48MHz 1.5 V; REF T 11 ICS9248-112 MIN TYP MAX UNITS 2.4 3.29 V 0.009 0.55 V -136 -33 mA -33 -13 30 115 0.5 1 0.5 1 ...

Page 12

... ICS9248-112 TOP VIEW A 2 SEE DETAIL “A” µ ° 0 Ordering Information ICS9248yF-112-T Example: ICS XXXX PPP - T 0326C— ...

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