lmx2505lq1321 National Semiconductor Corporation, lmx2505lq1321 Datasheet - Page 11

• Manufacturer Part Number: lmx2505lq1321
• Description: Pllatinu Dual Frequency Synthesizer System With Integrated Vcos
• Manufacturer: National Semiconductor Corporation

Programming Description
GENERAL PROGRAMMING INFORMATION
The serial interface has a 24-bit shift register to store the incoming data bits temporarily. The incoming data is first loaded into the
shift register from MSB to LSB. The data is shifted at the rising edge of the clock signal. When the latch enable signal transitions
from LOW to HIGH, the data stored in shift register is transferred to the proper register depending on the address bit setting. The
selection of the particular register is determined by the control bits indicated in boldface text.
At initial start-up, the MICROWIRE loading requires three default words (registers R2, loaded first, to R0, loaded last). After the
device has been initially programmed, the RF VCO frequency can be changed using a single register (R0).
The control register content map describes how the bits within each control register are allocated to the specific control functions.
NOTE: R0 control register will be used when hot start frequency change.
NOTE: Boldface text represent address bits.
R0
(Default)
R1
(Default)
R2
(Default)
R3
R4
R5
MSB
23
RX/
TX
SPI_
DEF
1
1
0
0
22
RF_
PD
0
1
0
0
0
21
HS 0
0
0
0
0
0
20 19
1
0
0
0
0
BS
0
1
0
0
0
18 17 16 15 14 13 12 11 10 9 8 7 6
0
0
1
0
0
1
0
1
1
0
RF_B
[3:0]
COMPLETE REGISTER MAP
0
0
0
1
0
SHIFT REGISTER BIT LOCATION
1
0
1
1
0
0
1
0
0
0
11
RF_A
[2:0]
0
1
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0 1 0 LD OB_
0 0 0 0
0 0 0 0
1 1 0 0
0 0 0 0
RF_FN
[9:0]
5
CRL
[1:0]
0
0
1
0
4
0
1
0
0
3
OSC_
FREQ
[1:0]
0
1
0
1
2
1
0
1
1
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1
0
0
1
1
1
1
LSB
0
0
1
0
1
1
1