lmx2505lq1321 National Semiconductor Corporation, lmx2505lq1321 Datasheet - Page 12

• Manufacturer Part Number: lmx2505lq1321
• Description: Pllatinu Dual Frequency Synthesizer System With Integrated Vcos
• Manufacturer: National Semiconductor Corporation

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Programming Description
R0 REGISTER
The R0 register address bits (R0 [1:0]) are “00”.
The Rx/Tx bit selects between receive and transmit modes and, in conjunction with the band select bit (BS), the channel spacing
to be synthesized.
The RF_PD bit selects the power down mode of the RF PLL and selected VCO.
The HS bit selects between normal and high speed locking mode.
The BS bit determines which of the two internal VCOs (PDC800 or PDC1500) is active.
The RF N counter consists of the 4-bit programmable counter (RF_B counter), the 3-bit swallow counter (RF_A counter) and the
10-bit delta sigma modulator (RF_FN counter). The equations for calculating the counter values are presented below.
R0
(Default)
Counter Name
Modulus Counter
Programmable Counter
Swallow Counter
MSB
23
RX/
TX
Name
RX/TX
RF_PD
HS
BS
RF_B [3:0]
RF_A [2:0]
RF_FN [9:0]
22
RF_
PD
21
HS
20
0
19
BS
18
(Continued)
Symbol
RF_FN
RF_B
RF_A
17
RF_B
[3:0]
SHIFT REGISTER BIT LOCATION
16
R0 REGISTER
15
Data Field
14
12
Functions
RX/TX Mode
0 = Rx
1 = Tx
Power Down of RF Synthesizer
0 = RF synthesizer on (Active mode)
1 = RF synthesizer powered down
Locking Mode
0 = Normal Mode
1 = High Speed Mode
Band Select
1 = RF1 VCO (PDC1500)
0 = RF2 VCO (PDC800)
RF_B Counter
4-bit programmable counter
0 ≤ RF_B ≤ 15 for both bands
RF_A Counter
3-bit swallow counter
0 ≤ RF_A ≤ 7 for PDC1500
0 ≤ RF_A ≤ 3 for PDC800
RF_FN Counter
10-bit modulus counter
0 ≤ RF_FN
RF_A
[2:0]
13
Functions
RF N Divider
N = 8 x RF_B + RF_A + RF_FN/FD (PDC1500)
N = 4 x RF_B + RF_A + RF_FN/FD (PDC800)
12
<
11
FD See Table 6 for FD values.
10
9
8
RF_FN
[9:0]
7
6
5
4
3
2
1
Address
Field
0
LSB
0
0