lmx2505lq1321 National Semiconductor Corporation, lmx2505lq1321 Datasheet - Page 14

• Manufacturer Part Number: lmx2505lq1321
• Description: Pllatinu Dual Frequency Synthesizer System With Integrated Vcos
• Manufacturer: National Semiconductor Corporation

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Programming Description
R1 REGISTER
The R1 register address bits (R1 [1:0]) are “01”.
The SPI_DEF bit allows for the programming of words R3 to R5. Under most circumstances, the SPI_DEF bit should be set to
1.
The LD bit sets the function of the lock detect pin. Enabling the lock detect function provides a digital lock detect output of the
active RF synthesizer at the LD pin.
The OB_CRL [1:0] bits determine the power level of the RF output buffer. The power level can be adjusted to best meet the
system requirement.
The reference frequency selection bits, OSC_FREQ [1:0], are used to set the reference clock and R divider for use with one of
the following reference frequencies: 12.6 MHz, 14.4 MHz, 25.2 MHz or 26.0 MHz. The LMX2505 uses the OSC_FREQ bits along
with the BS and RX/TX bits to determine the correct divide ratios needed to meet the required channel spacing for the mode of
operation selected. Refer to Table 6 for a summary of denominator values.
R1
(Default)
MSB
23
SPI_
DEF
Name
SPI_DEF
LD
OB_CRL [1:0]
OSC_FREQ [1:0]
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
0
0
1
0
0
1
(Continued)
0
SHIFT REGISTER BIT LOCATION
1
R1 REGISTER
Data Field
0
14
0
Functions
Default Register Selection
0 = OFF (Use values set in R0 to R5)
1 = ON (Use default values set in R0 to R2)
Lock Detect
0 = Disable (GND)
1 = Enable
Output Buffer Control
PDC1500, PDC800
00 = -10 dBm, -12 dBm
01 = -7 dBm, -8 dBm
10 = -4 dBm, -6 dBm
11 = -2 dBm, -3 dBm
Reference Frequency Selection
00 = 12.6 MHz
01 = 14.4 MHz
10 = 25.2 MHz
11 = 26.0 MHz
0
0
0
0 1 0 LD OB_
5
CRL
[1:0]
4
3
OSC_
FREQ
[1:0]
2
1
Address
Field
0
LSB
0
1