adf4351 Analog Devices, Inc., adf4351 Datasheet - Page 11

• Manufacturer Part Number: adf4351
• Description: Wideband Synthesizer With Integrated Vco Preliminary Technical Data Adf4351
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
during power-down.
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. The division ratio is determined by INT, FRAC and MOD
values, which build up this divider.
INT, FRAC, MOD, AND R COUNTER RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies
that are spaced by fractions of the PFD frequency. See the RF
Synthesizer—A Worked Example section for more information.
The RF VCO frequency (RF
where RF
controlled oscillator (VCO).
INT is the preset divide ratio of the binary 16-bit counter
(23 to 65535 for 4/5 prescaler, 75 to 65,535 for 8/9 prescaler).
MOD is the preset fractional modulus (2 to 4095).
FRAC is the numerator of the fractional division (0 to MOD − 1).
where:
REF
D is the REF
T is the REF
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
IN
RF
f
PFD
is the reference input frequency.
OUT
= REF
OUT
REF
= f
IN
IN
is the output frequency of external voltage
PFD
IN
divide-by-2 bit (0 or 1).
doubler bit.
IN
NC
× (INT + (FRAC/MOD))
× [(1 + D)/(R × (1 + T))]
POWER-DOWN
Figure 16. Reference Input Stage
SW1
CONTROL
NO
NC
SW3
SW2
OUT
100kΩ
) equation is
BUFFER
TO R COUNTER
IN
pin
Rev. PrC | Page 11 of 28
(1)
(2)
INT N MODE
If the FRAC = 0 and DB8 in Register 2 (LDF) is set to 1, the
synthesizer operates in integer-N mode. The DB8 in Register 2
(LDF) should be set to 1 to get integer-N digital lock detect.
R COUNTER
The 10–bit R counter allows the input reference frequency
(REF
to the PFD. Division ratios from 1 to 1023 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The phase frequency detector (PFD) takes inputs from the
R counter and N counter and produces an output proportional
to the phase and frequency difference between them. Figure is
a simplified schematic of the phase frequency detector. The
PFD includes a programmable delay element that sets the width
of the anti-backlash pulse. This is controlled by bit DB22,
register 3, which if set to ‘0’ programs a 6 ns delay for Fractional-
N applications or if programmed with a ‘1’ programs a 3 ns delay
for Integer-N applications. This pulse ensures there is no dead
zone in the PFD transfer function.
OUTPUT DIVIDERS
VCO OUTPUT/
+IN
–IN
HIGH
HIGH
IN
) to be divided down to produce the reference clock
FROM
D2
D1
CLR1
CLR2
U1
U2
RF N DIVIDER
Figure 18. PFD Simplified Schematic
Q1
N COUNTER
Q2
REG
INT
UP
DOWN
Figure 17. RF INT Divider
DELAY
U3
MOD
REG
N = INT + FRAC/MOD
INTERPOLATOR
THIRD-ORDER
FRACTIONAL
CHARGE
PUMP
VALUE
FRAC
ADF4351
TO PFD
CP