adf4351 Analog Devices, Inc., adf4351 Datasheet - Page 21

• Manufacturer Part Number: adf4351
• Description: Wideband Synthesizer With Integrated Vco Preliminary Technical Data Adf4351
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
INITIALIZATION SEQUENCE
The following sequence of registers is the correct sequence for
initial power-up of the ADF4351 after the correct application of
voltages to the supply pins:
•
•
•
•
•
•
RF SYNTHESIZER—A WORKED EXAMPLE
The following is an example how to program the ADF4351
synthesizer:
where:
RF
INT is the integer division factor.
FRAC is the fractionality.
MOD is the modulus.
RF divider is the output divider that divides down the VCO
frequency.
where:
REF
D is the RF REF
T is the reference divide-by-2 bit (0 or 1).
R is the RF reference division factor.
For example, in a UMTS system, where 2112.6 MHz RF
frequency output (RF
frequency input (REF
resolution (f
4.4 GHz. Therefore, the RF divider of 2 should be used (VCO
frequency = 4225.2 MHz, RF
4225.2 MHz/2 = 2112.6 MHz).
It is also important where the loop is closed. In this example,
the loop is closed (see Figure ).
the ADF4351 operates in the frequency range of 2.2 GHz to
OUT
IN
Register 5
Register 4
Register 3
Register 2
Register 1
Register 0
RF
f
PFD
is the RF frequency output.
is the reference frequency input.
OUT
= REF
f
PFD
= [INT + (FRAC/MOD)] × [f
RESOUT
Figure 30. Loop Closed Before Output Divider
IN
IN
× [(1 + D)/(R × (1+T))]
) is required on the RF output. Note that
doubler bit.
PFD
OUT
IN
DIVIDER
) is available, and a 200 kHz channel
) is required, a 10 MHz reference
N
OUT
VCO
= VCO frequency/RF divider =
PFD
÷2
]/RF divider
RF
OUT
Rev. PrC | Page 21 of 28
(3)
(4)
Channel resolution (f
of the RF divider. Therefore, channel resolution at the output of
the VCO (f
From Equation 4,
where:
INT = 422
FRAC = 13
MODULUS
The choice of modulus (MOD) depends on the reference signal
(REF
the RF output. For example, a GSM system with 13 MHz REF
sets the modulus to 65. This means the RF output resolution (f
is the 200 kHz (13 MHz/65) necessary for GSM. With dither off,
the fractional spur interval depends on the modulus values chosen
(see Table 6).
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on-chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the
noise performance of the system. Doubling the PFD frequency
usually improves noise performance by 3 dB. It is important to
note that the PFD cannot operate above 32 MHz due to a limi-
tation in the speed of the Σ-Δ circuit of the N-divider.
The reference divide-by-2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency. This is necessary
for the correct operation of the cycle slip reduction (CSR)
function. See the Cycle Slip Reduction for Faster Lock Times
section for more information.
12-BIT PROGRAMMABLE MODULUS
Unlike most other fractional-N PLLs, the ADF4351 allows the
user to program the modulus over a 12–bit range. This means
the user can set up the part in many different configurations for
the application, when combined with the reference doubler and
the 10-bit R counter.
For example, consider an application that requires 1.75 GHz RF
and 200 kHz channel step resolution. The system has a 13 MHz
reference signal.
One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65. This results in
the required 200 kHz resolution.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. This 26 MHz is then fed
into the PFD programming the modulus to divide by 130. This
also results in 200 kHz resolution and offers superior phase
noise performance over the previous setup.
MOD = REF
MOD = 10 MHz/400 kHz = 25
f
2112.6 MHz = 10 MHz × (INT + FRAC/25)/2
IN
PFD
) available and the channel resolution (f
= [10 MHz × (1 + 0)/1] = 10 MHz
RES
) is to be twice the f
IN
/f
RES
RESOUT
) or 200 kHz is required at the output
RESOUT
, that is 400 kHz.
RES
) required at
ADF4351
IN
RES
(5)
(6)
)