adf4351 Analog Devices, Inc., adf4351 Datasheet - Page 26

• Manufacturer Part Number: adf4351
• Description: Wideband Synthesizer With Integrated Vco Preliminary Technical Data Adf4351
• Manufacturer: Analog Devices, Inc.

ADF4351
INTERFACING
The ADF4351 has a simple SPI-compatible serial interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When LE goes high, the 32 bits that have been clocked
into the appropriate register on each rising edge of CLK are
transferred to the appropriate latch. See Figure 2 for the timing
diagram and Table 5 for the register address table.
ADuC812 Interface
Error! Reference source not found.Figure 35 shows the
interface between the ADF4351 and the ADuC70xx family of
analog microcontrollers. The ADuC70xx family is based on an
AMR7 core, although the same interface can be used with any
8051-based microcontroller. The microcontroller is set up for
SPI master mode with CPHA = 0. To initiate the operation, the
I/O port driving LE is brought low. Each latch of the ADF4351
needs a 32-bit word. This is accomplished by writing four 8-bit
bytes from the microcontroller to the device. When the last byte
is written, the LE input should be brought high to complete
the transfer.
On first applying power to the ADF4351, it needs six writes
(one each to R5, R4, R3, R2, R1, R0) for the output to become
active.
I/O port lines on the microcontroller are also used to control
power-down (CE input) and to detect lock (MUXOUT
configured as lock detect and polled by the port input).
When operating in the mode described, the maximum SPI
transfer rate of the ADuC7023 is 20Mbps. This means that
the maximum rate at which the output frequency can be
changed is 833 kHz. If using a faster SPI clock just make sure
the SPI timing requirements listed in Table 2 are adhered to.
ADuC70xx
I/O PORTS
Figure 35. ADuC7020-to-ADF4351 Interface
SCLOCK
MOSI
DATA
CLK
LE
CE
MUXOUT
(LOCK DETECT)
ADF4351
Rev. PrC | Page 26 of 28
ADSP-21xx Interface
Figure 36 shows the interface between the ADF4351 and the
Blackfin ADSP-BF527 digital signal processor (DSP). The
ADF4351 needs a 32-bit serial word for each latch write. The
easiest way to accomplish this using the Blackfin family is to use
the autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for 8 bits and use three memory locations for each 32-bit
word. To program each 32-bit latch, store the four 8-bit bytes,
enable the autobuffered mode, and write to the transmit register
of the DSP. This last operation initiates the autobuffer transfer.
As in the microcontroller case just make sure the clock speeds
are within the maximum limits outlined in table 2.
PCB DESIGN GUIDELINES FOR A CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-32-2) are rectangular.
The PCB pad for these is to be 0.1 mm longer than the package
land length and 0.05 mm wider than the package land width.
The land is to be centered on the pad. This ensures the solder
joint size is maximized. The bottom of the chip scale package
has a central thermal pad.
The thermal pad on the PCB is to be at least as large as the
exposed pad. On the PCB, there is to be a minimum clearance
of 0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
the thermal performance of the package. If vias are used, they
are to be incorporated in the thermal pad at 1.2 mm pitch grid.
The via diameter is to be between 0.3 mm and 0.33 mm, and the
via barrel is to be plated with 1 oz. of copper to plug the via.
ADSP-
BF527
I/O FLAGS

Figure 36. ADSP-BF527-to-ADF4351 Interface
MOSI
GPIO
SCK
Preliminary Technical Data
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
ADF4351