mc145425 Freescale Semiconductor, Inc, mc145425 Datasheet - Page 12

• Manufacturer Part Number: mc145425
• Description: Isdn Universal Digital Loop Transceivers
• Manufacturer: Freescale Semiconductor, Inc

* See Switching Characteristics waveforms.
MC145421 MC145425
12
Master Timing
Slave Timing
SE Pin Timing
SWITCHING CHARACTERISTICS
No.*
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
11
1
2
3
4
5
6
7
8
9
TDC/RDC Pulse Width High
TDC/RDC Pulse Width Low
MSI Rising Edge to TDC/RDC Falling Edge
MSI Pulse Width
MSI Rising Edge to First DCLK Falling Edge
MSI Rising Edge to First D1O, D2O Bit Valid
TE1, TE2 Rising Edge to TDC/RDC Falling Edge
TDC/RDC Falling Edge to TE1, TE2 Rising Edge
TE1, TE2 Rising Edge to First Tx Data Bit Valid
TDC/RDC Rising Edge to Tx Data Bits 2 Through 8 Valid
TE1, TE2 Falling Edge to Tx High–Impedance
REI, RE2 Rising Edge to TDC/RDC Falling Edge
TDC/RDC Falling Edge to RE1, RE2 Rising Edge
Rx Data Setup (Data Valid Before TDC/RDC Falling Edge)
Rx Data Hold (Data Valid After TDC/RDC Falling Edge)
RE1, RE2 Pulse Width
DCLK Rising Edge to D1O, D2O Bit Valid
D1I, D2I Data Setup (Data Valid Before DCLK Falling Edge)
D1I, D2I Data Hold (Data Valid After DCLK Falling Edge)
DCLK Pulse Width Low
DCLK Pulse Width High
MSI Rising Edge to VD Valid
PD, LB Setup (PD, LB Valid Before MSI Rising Edge)
PD, LB Hold (PD, LB Valid After MSI Rising Edge)
BCLK Pulse Width High (CCI = 8.192 MHz)
BCLK Pulse Width Low (CCI = 8.192 MHz)
EN1 or EN2 Rising Edge to BCLK Rising Edge
EN1 or EN2 Rising Edge to DCLK Rising Edge
EN1 or EN2 Rising Edge to First Tx Data Bit Valid
BCLK Rising Edge to Tx Data Bits 2 Through 8 Valid
DCLK Pulse Width High (CCI = 8.192 MHz)
DCLK Pulse Width Low (CCI = 8.192 MHz)
DCLK Rising Edge to D1O, D2O Bits Valid
Rx Setup (Rx Data Valid Before BCLK Falling Edge)
Rx Hold (Rx Data Valid After BCLK Falling Edge)
D1I, D2I Setup (D1I, D2I Valid Before DCLK Falling Edge)
D1I, D2I Hold (D1I, D2I Valid After DCLK Falling Edge)
EN1 Rising Edge to VD Valid
LB, PD Hold (LB, PD Valid After SE Falling Edge)
D1O, D2O, VD High Impedance After SE Falling Edge
D1O, D2O, VD Valid After SE Rising Edge
LB, PD Setup (LB, PD Valid Before SE Rising Edge)
(V DD = 5 V, T A = 0 to 70 C; C Load = 50 pF)
Parameter
3.66
3.66
31.0
31.0
Min
110
110
200
110
110
220
110
110
175
90
90
20
20
50
20
50
20
50
20
75
20
50
20
20
60
50
—
—
—
—
—
—
—
—
—
—
—
—
Max
4.15
4.15
– 75
31.5
31.5
100
135
150
175
50
50
70
50
50
50
70
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
MOTOROLA
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s