mc145425 Freescale Semiconductor, Inc, mc145425 Datasheet - Page 9

• Manufacturer Part Number: mc145425
• Description: Isdn Universal Digital Loop Transceivers
• Manufacturer: Freescale Semiconductor, Inc

third MSI following the last received burst. This is equivalent
to two MSI frames. The VD output is forced low during time–
out. The B channel output data will be unknown, but the
D channel bits will remain at their last values. Successful de-
modulation of a burst from the slave will result in leaving the
time–out state on the next rising MSI edge.
time–out controls the pin. Time–out forces the PD output low
to indicate that the device has powered itself down. In this
case, the slave will not transmit to the master. However,
MOTOROLA
In the master, time–out begins on the rising edge of the
When the PD pin is used as an output on the slave UDLT,
D1O, D2O
TDC/RDC
D1I, D2I
DCLK
RE1
RE2
TE1
TE2
MSI
VD
Rx
Tx
B CHANNEL 1 OUTPUT
Figure 1. Typical MC145421 Master ISDN UDLT Timing
DON’T CARE
1ST BIT
1ST BIT
B CHANNEL 1 INPUT
HIGH–Z
125 s
when a valid burst is received, time–out ends and the PD pin
is driven high to indicate power up. This feature allows the
slave UDLT to self–power–up and down in demand–powered
loop systems.
The slave uses a free running clock during time–
out. After a long period without a burst from the
master, the timing between master and slave
could be such that more than one burst will be
needed to resync the two devices.
B CHANNEL 2 OUTPUT
B CHANNEL 2 INPUT
2ND BIT
2ND BIT
NOTE
MC145421 MC145425
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