mc145425 Freescale Semiconductor, Inc, mc145425 Datasheet - Page 7

• Manufacturer Part Number: mc145425
• Description: Isdn Universal Digital Loop Transceivers
• Manufacturer: Freescale Semiconductor, Inc

Mu/A
Tone Format Input (Pin 11)
wave tone generated when the TONE input is high — Mu–
Law (Mu/A = 1) or CCITT A–Law (Mu/A = 0) format.
TONE
Tone Enable Input (Pin 16)
to be inserted in place of the demodulated B channel data on
B channel 1. This feature allows the designer to provide
audio feedback for telset keyboard operations.
PD
Power Down Input/Output (Pin 12)
it can be externally overdriven. When held low, the ISDN
UDLT is powered down, and the only active circuitry is that
which is necessary for demodulation, generation of EN1,
EN2, BCLK, and DCLK, and outputting of the data bits and
VD. When held high, the ISDN UDLT is powered up and
transmits normally in response to received bursts from the
master. If the ISDN UDLT is powered up for 250 s — which
is derived from an internal oscillator and no bursts from the
master have occurred — the ISDN slave UDLT generates
a free–running set of EN1, EN2, BCLK, and DCLK signals
and sends a burst to the master device every other 125 s
frame. This is a wake–up signal to the master.
ulated, the weak output drivers will try to force PD high. It will
try to force PD low if 250 s have elapsed without a burst
from the master being successfully demodulated. This allows
the slave device to self power up and down in demand–
powered loop systems.
CCI
Crystal Input (Pin 17)
and the XTL pin. A 10 M resistor between CCI and XTL and
25 pF capacitors from CCI and XTL to V SS are required to
ensure stability and start–up. CCI may also be driven with an
external 8.192 MHz signal if a crystal is not desired.
XTL
Crystal Output (Pin 18)
15 pF of additional load capacitance.
D1I, D2I
D Channel Inputs (Pins 6, 7)
The D channel data bits are clocked in serially on the nega-
tive edge of the 16 kbps DCLK output pin.
D1O, D2O
D Channel Outputs (Pins 9, 10)
nels. These pins are updated on the rising edges of the slave
DCLK output pin.
MOTOROLA
This pin determines the PCM code for the 500 Hz square
A high on this pin causes a 500 Hz square wave PCM tone
This is a bidirectional pin with a weak output driver so that
When PD is floating and a burst from the master is demod-
Normally, an 8.192 MHz crystal is tied between this pin
This pin is capable of driving one external CMOS input and
These two pins are inputs for the 16 kbps D data channels.
These two pins are outputs for the 16 kbps D data chan-
Tx
Transmit Data Output (Pin 13)
the master. B channel 1 data is output on the first eight cycles
of the BCLK output when EN1 is high. B channel 2 data is
output on the next eight cycles of the BCLK, when EN2 is
high. B channel data bits are clocked out on the rising edge
of the BCLK output pin.
DCLK
D Channel Clock Output (Pin 8)
D channels. It starts upon demodulation of a burst from the
master device. This signal is rising edge aligned with the
EN1 and BCLK signals. After the demodulation of a burst,
the DCLK line completes two cycles and then remains low
until another burst from the master is demodulated. In this
manner synchronization with the master is established and
any clock slip between master and slave is absorbed each
frame.
Rx
Receive Data Input (Pin 21)
data is clocked in on the first eight falling edges of the BCLK
output following the rising edge of the EN1 output. B channel
2 data is clocked in on the next eight falling edges of the
BCLK following the rising edge of the EN2 output.
EN1
B Channel 1 Enable Output (Pin 15)
of the B channel 1 data. While EN1 is high, B channel 1 data
is clocked out on the Tx pin on the first eight rising edges of
the BCLK. During this same time, B channel 1 input data is
clocked in on the Rx pin on the first eight falling edges of the
BCLK. The VD pin is also updated on the rising edge of the
EN1 signal. EN1 serves as the slave device’s 8 kHz frame
reference signal.
EN2
B Channel 2 Enable Output (Pin 14)
to signal the time slot for the input and output of data for the
B channel 2 data.
BCLK
B Channel Data Clock Output (Pin 20)
clock for the B channel data. This clock signal is 128 kHz and
begins operating upon the successful demodulation of a
burst from the master. At this time, EN1 goes high and BCLK
starts toggling. BCLK remains active for 16 periods, at the
end of which time it remains low until another burst is re-
ceived from the master. In this manner synchronization be-
tween the master and slave is established and any clock
slippage is absorbed each frame.
This line is an output for the B channel data received from
This output is the transmit and receive data clock for both
This pin is an input for the B channel data. B channel 1
This line is an 8 kHz enable signal for the input and output
This pin is the logical inverse of the EN1 output and is used
This is a standard B series output which provides the data
MC145421 MC145425
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