pcf8811 NXP Semiconductors, pcf8811 Datasheet - Page 58

• Manufacturer Part Number: pcf8811
• Description: 80 X 128 Pixels Matrix Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
22.5.2
The action of the ‘Refresh’ instruction is to force the OTP
shift register to re-load from the non-volatile OTP cells.
This instruction takes up to 5 ms to complete. During this
time all other instructions may be sent.
In the PCF8811 the ‘Refresh’ instruction is associated with
the ‘Power control’ instruction so that the shift register is
automatically refreshed every time the high voltage
generator is enabled or disabled. It should be noted
however, that if this instruction is sent while in the
power-save mode, the PC[1:0] bits will be updated but the
refreshing will be ignored.
22.6
An example of the sequence of commands and data is
shown in Table 25. In this example the shift register is filled
with the following data: MMVOPCAL = 4 (11100 BIN),
MMTC = 2 (010 BIN) and the seal bit is 0.
Table 25 Example sequence for filling the shift register; note 1
Notes
1. X = don’t care.
2. The data for the bits is not in the correct shift register position until all bits have been sent.
2004 May 17
1
2
3
4
5
6
7
8
9
10
11
12
An alternative ending could be to stay in CALMM mode
13
STEP EXT
80
Example of filling the shift register
R
128 pixels matrix LCD driver
EFRESH
X
X
X
X
X
X
X
X
X
X
X
X
D/C
0
0
0
0
0
0
0
0
0
0
0
0
R/W
0
0
0
0
0
0
0
0
0
0
0
0
D7
1
1
1
1
1
1
1
1
1
1
0
1
D6
X
X
X
X
X
X
X
X
X
X
1
0
D5
X
X
X
X
X
X
X
X
X
X
1
0
D4
X
X
X
X
X
X
X
X
X
X
0
0
D3
58
X
X
X
X
X
X
X
X
X
X
0
0
It is assumed that the PCF8811 has just been reset. After
transmitting the last bit the PCF8811 can exit or remain in
the CALMM mode (see step 1). It should be noted that
while in CALMM mode the interface does not recognize
commands in the normal sense.
After this sequence has been applied it is possible to
observe the impact of the data shifted in. The described
sequence is, however, not useful for OTP programming
because the number of bits with the value logic 1 is greater
than that allowed for programming; see Section 22.7.
Figure 49 shows the shift register after this action.
D2
X
X
X
X
X
X
X
X
X
X
0
0
D1
X
X
X
X
X
X
X
X
X
X
0
1
D0
1
0
1
1
1
0
0
0
1
0
0
0
exit Power-down
wait 5 ms for refresh to take effect
enter CALMM mode
shift in data. MMVOPCAL[4] is first
bit; note 2
MMVOPCAL[3]
MMVOPCAL[2]
MMVOPCAL[1]
MMVOPCAL[0]
MMTC[2]
MMTC[1]
MMTC[0]
seal bit; exit CALMM mode
seal bit; remain in CALMM mode
ACTION
Product specification
PCF8811