cdp68hc68p1 Intersil Corporation, cdp68hc68p1 Datasheet - Page 5

• Manufacturer Part Number: cdp68hc68p1
• Description: Cmos Serial 8-bit Input/output Port
• Manufacturer: Intersil Corporation

Waveforms
NOTE: CPOL and CPHA are bits in the CDP68HC05C4B and
CDP68HC05C16B MCU control register and determine inactive
clock polarity and phase. CPHA must always equal 1.
MISO
MOSI
CE
SCK
FIGURE 5. DATA TRANSFERS UTILIZING CLOCK INPUT
MISO
MOSI
SCK
CE
(CPOL = 1)
(CPOL = 0)
MOSI
MISO
SCK
SCK
CE
CE
X
OR
X
HI Z
HI Z
C07
t
EVCV
C07
t
EVCV
t
WL
t
WL
t
DVCV
5
SHIFT INTERNAL
SHIFT INTERNAL
C06
C06
MSB
STROBE
STROBE
t
WH
t
FIGURE 4. READ CYCLE TIMING WAVEFORMS
WH
C05
MSB - 1
C07
C07
C05
FIGURE 3. PORT-PIN DATA CHANGES
t
CVQX
t
CVDV
C04
C06
C06
C04
CDP68HC68P1
t
CVDX
C00
COMPARE FLAG
COMPARE FLAG
C00
Introduction
The single port I/O is serially accessed via the synchronous
SPI bus. It features 8 data pins that are programmed as
inputs or outputs. Serial access consists of a two-byte
operation. The first byte shifted in is the control byte that
configures the device. The second byte transferred is the
data byte that is read from or written to the data register or
data direction register. This data byte can also be
programmed to act as a mask to set or clear individual bits.
Functional Description
The single port I/O consists of three byte-wide registers,
(data direction, data and shift) an input/output buffer and
control logic circuitry (See Figure 1). Data is transferred
between the I/O data and data direction registers via the shift
register. Once the I/O port is selected, the first byte shifted in
to the shift register is the control byte that selects the register
(the Data or Data direction register), determines data
transfer direction (read or write) and sets the compare
t
t
REC
REC
t
DVCV
D7
D7
D7
D6
D6
D6
t
X
CVDX
t
r
, t
f
t
EXQZ
D0
D0
D0
t
t
CVEX
CVEX
X
HI Z
HI Z