uda1344ts-n2 NXP Semiconductors, uda1344ts-n2 Datasheet - Page 6

• Manufacturer Part Number: uda1344ts-n2
• Description: Low-voltage Low-power Stereo Audio Codec With Dsp Features
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
The UDA1344TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system clock must be
locked in frequency to the digital interface input signals.
The BCK clock can be up to 128f
BCK frequency is 128 times the Word Select (WS)
frequency or less: f
Remarks:
1. The WS edge MUST fall on the negative edge of the
2. The sampling frequency range is from 8 to 55 kHz
3. For MSB- and LSB-justified formats it is important to
Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1344TS consists of two
3rd-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The oversampling ratio is 128.
In contrast to the UDA1340M, the UDA1344TS supports
1 V (RMS) input signals and can be set, via an external
resistor, to support 2 V (RMS) input signals.
Analog front-end
The analog front-end is equipped with a selectable 0 dB or
6 dB gain block. The pin to select the gain switch is given
in Section “L3 mode”. This block can be used in
applications in which both 1 V (RMS) and 2 V (RMS) input
signals are available.
In applications in which a 2 V (RMS) input signal is used,
a 12 k resistor must be connected in series with the input
of the ADC. This makes a voltage divider with the internal
ADC resistor and makes sure only 1 V (RMS) maximum is
input to the IC. Using this application for a 2 V (RMS) input
signal, the gain switch must be set to 0 dB. When a
1 V (RMS) input signal is input to the ADC in the same
application, the gain switch must be set to 6 dB.
An overview of the maximum input voltages allowed
against the presence of an external resistor and the setting
of the gain switch is given in Table 1.
2001 Jun 29
Low-voltage low-power stereo audio
CODEC with DSP features
BCK clock at all times for proper operation of the digital
I/O data interface
have a WS signal with a duty factor of 50%.
BCK
= < 128
s
f
, or in other words the
WS
.
6
Table 1 Application modes using input gain stage
Decimation filter (ADC)
The decimation from 128f
The first stage realizes 3rd-order
filter decreases the sample rate by 16.
The second stage, a Finite Impulse Response (FIR) filter,
consists of 3 half-band filters, each decimating by a factor
of 2.
Table 2 Decimation filter characteristics
DC-cancellation filter (ADC)
An optional Infinite Impulse-Response (IIR) high-pass filter
is provided to remove unwanted DC components.
The operation is selected by the microcontroller via the
L3 interface. The filter characteristics are given in Table 3.
Table 3 DC-cancellation filter characteristics
Present
Present
Absent
Absent
Pass-band ripple
Stop band
Dynamic range
Overall gain with
0 dB input to the
ADC
Pass-band ripple
Pass-band gain
Droop
Attenuation at DC
Dynamic range
RESISTOR
(12 k )
ITEM
ITEM
CONDITIONS
INPUT GAIN
at 0.00000036f
0
0
CONDITIONS
SWITCH
>0.55f
at 0.00045f
s
0 dB
6 dB
0 dB
6 dB
0
to 1f
DC
0.45f
0.45f
0.45f
s
s
is performed in 2 stages.
sin x
----------- -
s
s
x
s
UDA1344TS
s
Product specification
characteristic. This
s
0.5 V (RMS)
VALUE (dB)
MAXIMUM
2 V (RMS)
1 V (RMS)
1 V (RMS)
VALUE (dB)
VOLTAGE
INPUT
108
0.031
0.05
1.16
none
>110
>40
60
0