stmpe610 STMicroelectronics, stmpe610 Datasheet - Page 13

• Manufacturer Part Number: stmpe610
• Description: Advanced Touch Screen Controller With 6-bit Port Expander
• Manufacturer: STMicroelectronics

STMPE610
5.1.2
5.1.3
5.2
Register write
The following steps need to be followed for register write through SPI.
1.
2.
3.
4.
5.
Termination of data transfer
A transfer can be terminated before the last launch edge by deasserting the CS_n signal. If
the last launch clock is detected, it is assumed that the data transfer is successful.
SPI timing modes
The SPI timing modes are defined by CPHA and CPOL,CPHA and CPOL are read from the
"SDAT" and "A0" pins during power-up reset. The following four modes are defined
according to this setting.
Table 9.
The clocking diagrams of these modes are shown in ON reset. The device always operates
in mode 0. Once the bits are set in the SPICON register, the mode change takes effect on
the next transaction defined by the CS_n pin being deasserted and asserted.
CPOL_N (SDAT pin)
Assert CS_n by driving a '0' on this pin.
Drive a '0' on the first SCL launch clock on MOSI to select a write operation.
The next 7 bits on MOSI denote the 7-bit register address (MSB first).
The next byte on the MOSI denotes data to be written.
The following transmissions on MOSI are considered byte-sized data. The register
address to which the following data is written depends on whether the autoincrement
bit in the SPICON register is set. If this bit has been set previously, the register address
is incremented for data writes.
1
1
0
0
SPI timing modes
CPOL
0
0
1
1
CPHA (ADDR pin)
0
1
0
1
Mode
SPI interface
0
1
2
3
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