pca9506dgg NXP Semiconductors, pca9506dgg Datasheet
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pca9506dgg Summary of contents
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PCA9505/06 40-bit I Rev. 03 — 6 June 2007 1. General description The PCA9505/PCA9506 provide 40-bit parallel input/output (I/O) port expansion for 2 I C-bus applications organized in 5 banks of 8 I/Os supply voltage, the outputs ...
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... I Gaming machines I Instrumentation and test measurement 4. Ordering information Table 1. Ordering information Type number Topside mark PCA9505DGG PCA9505DGG PCA9506DGG PCA9506DGG PCA9506BS PCA9506BS PCA9505_9506_3 Product data sheet 40-bit I and power-up 3-state) OFF Package Name Description TSSOP56 plastic thin shrink small outline package; 56 leads; ...
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... NXP Semiconductors 5. Block diagram SCL SDA RESET Fig 1. Block diagram of PCA9505/06 PCA9505_9506_3 Product data sheet PCA9505/PCA9506 LOW PASS INPUT FILTERS POWER-ON RESET All I/Os are set to inputs at power-up and RESET. Rev. 03 — 6 June 2007 PCA9505/06 2 40-bit I C-bus I/O port with RESET, OE and INT ...
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... NXP Semiconductors write configuration Fig 2. Simplified schematic of IO0_0 to IO4_7 PCA9505_9506_3 Product data sheet I/O configuration register data from D Q shift register CK Q pulse data from D Q shift register write pulse CK output port register read pulse data from shift register write polarity pulse On power-up or RESET, all registers return to default values ...
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... C-bus I/O port with RESET, OE and INT 1 SDA SCL 2 IO0_0 3 4 IO0_1 5 IO0_2 IO0_3 7 8 IO0_4 IO0_5 9 IO0_6 IO0_7 IO1_0 13 IO1_1 14 PCA9505DGG PCA9506DGG 15 IO1_2 IO1_3 16 IO1_4 IO1_5 IO1_6 20 IO1_7 21 22 IO2_0 IO2_1 24 IO2_2 25 26 IO2_3 Rev. 03 — 6 June 2007 ...
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... NXP Semiconductors Fig 4. Pin configuration for HVQFN56 6.2 Pin description Table 2. Symbol SDA SCL IO0_0 to IO0_7 IO1_0 to IO1_7 IO2_0 to IO2_7 IO3_0 to IO3_7 IO4_0 to IO4_7 PCA9505_9506_3 Product data sheet 40-bit I terminal 1 index area IO0_4 1 2 IO0_5 IO0_6 ...
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... NXP Semiconductors Table 2. Symbol OE INT RESET [1] HVQFN package die supply ground is connected to both V be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region ...
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... NXP Semiconductors The lowest 6 bits are used as a pointer to determine which register will be accessed. The registers are: • IP: Input Port registers (5 registers) • OP: Output Port registers (5 registers) • PI: Polarity Inversion registers (5 registers) • IOC: I/O Configuration registers (5 registers) • MSK: Mask interrupt registers (5 registers) If the Auto-Increment fl ...
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... NXP Semiconductors 7.3 Register definitions Table 3. Register summary Register # (hex) Input Port registers Output Port registers ...
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... NXP Semiconductors Table 3. Register summary …continued Register # (hex) Mask Interrupt registers 7.3.1 IP0 to IP4 - Input Port registers These registers are read-only. They reflect the incoming logic levels of the port pins regardless of whether the pin is defi ...
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... NXP Semiconductors 7.3.2 OP0 to OP4 - Output Port registers These registers reflect the outgoing logic levels of the pins defined as outputs by the I/O Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from these registers reflect the values that are in the flip-flops controlling the output selection, not the actual pin values. Ox[ IOx_y = 0 if IOx_y defi ...
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... NXP Semiconductors 7.3.4 IOC0 to IOC4 - I/O Configuration registers These registers configure the direction of the I/O pins. Cx[ The corresponding port pin is an output. Cx[ The corresponding port pin is an input. Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7). ...
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... NXP Semiconductors 7.6 Interrupt output (INT) The open-drain active LOW interrupt is activated when one of the port pins changes state and the port pin is configured as an input and the interrupt not masked. The interrupt is deactivated when the port pin input returns to its previous state or the Input Port register is read ...
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... NXP Semiconductors 8. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 9. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse ...
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SDA output bank START condition register bank 0 R selected acknowledge from slave acknowledge ...
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SDA START condition R acknowledge from slave The programming becomes effective at the acknowledge. Less ...
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... NXP Semiconductors 9. Application design-in information V DD 1 (optional) MASTER CONTROLLER SCL SDA RESET INT OE GND Device address configured as 0100 000X for this example. IO0_0, IO0_2, IO0_3, IO1_0 to IO3_7 are configured as outputs. IO0_1, IO0_4, IO4_0 to IO4_7 configured as inputs. ...
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... NXP Semiconductors 10. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V input voltage I I input current I V input/output voltage on any other pin I/O(n) V input/output voltage on pin IO0_n I/O(IO0n) I output current on an I/O pin ...
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... NXP Semiconductors Table 10. Static characteristics Symbol Parameter Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I leakage current L C input capacitance i I/Os V LOW-level input voltage IL V HIGH-level input voltage ...
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... NXP Semiconductors 12. Dynamic characteristics Table 11. Dynamic characteristics Symbol Parameter f SCL clock frequency SCL t bus free time between a STOP and BUF START condition t hold time (repeated) START HD;STA condition t set-up time for a repeated START SU;STA condition t set-up time for STOP condition SU;STO ...
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... NXP Semiconductors [5] The maximum t for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t f 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specifi ...
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... NXP Semiconductors START SCL SDA RESET rec(rst) IOx_y Fig 18. Reset timing 13. Test information Fig 19. Test circuitry for switching times PCA9505_9506_3 Product data sheet PULSE GENERATOR R = load resistance load capacitance includes jig and probe capacitance termination resistance should be equal to the output impedance Z T generators ...
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... NXP Semiconductors 14. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 0.85 mm terminal 1 index area terminal 1 56 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0.30 mm 0.2 1 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 15. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling integrated circuits. 16. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 22. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 17. Abbreviations Table 14. Acronym CDM DUT ESD HBM C-bus LED MM PLC POR PWM RAID ...
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... Release date PCA9505_9506_3 20070606 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added device PCA9505 • Section 1 “General – ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 Command register . . . . . . . . . . . . . . . . . . . . . . 7 7.3 Register definitions . . . . . . . . . . . . . . . . . . . . . . 9 7.3.1 IP0 to IP4 - Input Port registers . . . . . . . . . . . 10 7.3.2 OP0 to OP4 - Output Port registers . . . . . . . . 11 7.3.3 PI0 to PI4 - Polarity Inversion registers 7.3.4 IOC0 to IOC4 - I/O Confi ...