ca3304 Intersil Corporation, ca3304 Datasheet

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ca3304

Manufacturer Part Number
ca3304
Description
4-bit, 25 Msps, Flash A/d Converters
Manufacturer
Intersil Corporation
Datasheet

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August 1997
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• CMOS/SOS Low Power with Video Speed (Typ) . . 25mW
• Parallel Conversion Technique
• Single Power Supply Voltage . . . . . . . . . . . . 3V to 7.5V
• 25MHz Sampling Rate (40ns Conversion Time) at 5V
• 4-Bit Latched Three-State Output with Overflow and
• Inherent Resistance to Latch-Up Due to SOS Process
• Bipolar Input Range with Optional Second Supply
• Wide Input Bandwidth (Typ) . . . . . . . . . . . . . . . . 25MHz
Applications
• High Speed A/D Conversion
• Ultrasound Signature Analysis
• Transient Signal Analysis
• High Energy Physics Research
• General-Purpose Hybrid ADCs
• Optical Character Recognition
• Radar Pulse Analysis
• Motion Signature Analysis
• Robot Vision
• RSSI Circuits
Ordering Information
Pinout
CA3304E
CA3304AE
CA3304M
CA3304AM
CA3304D
CA3304AD
PART NUMBER LINEARITY (INL, DNL)
Supply
Data Change Outputs
1
/
8
LSB Maximum Nonlinearity (A Version)
0.125 LSB
0.125 LSB
0.125 LSB
0.25 LSB
0.25 LSB
0.25 LSB
DATA CHANGE (DC)
OVERFLOW (OF)
BIT 1 (LSB)
SAMPLING RATE
25MHZ (40ns)
25MHz (40ns)
25MHz (40ns)
25MHz (40ns)
25MHz (40ns)
25MHz (40ns)
BIT 2
BIT 3
BIT 4
CE2
V
CA3304 (SBDIP, PDIP, SOIC)
CA3304, CA3304A
SS
1
2
3
4
5
6
7
8
TOP VIEW
4-7
Description
The Intersil CA3304 is a CMOS parallel (FLASH) analog-to-
digital converter designed for applications demanding both
low-power consumption and high speed digitization. Digitiz-
ing at 25MHz, for example, requires only about 35mW.
The CA3304 operates over a wide, full-scale signal input
voltage range of 0.5V up to the supply voltage. Power
consumption is as low as 10mW, depending upon the clock
frequency selected.
The intrinsic high conversion rate makes the CA3304 types
ideally suited for digitizing high speed signals. The overflow
bit makes possible the connection of two or more CA3304s
in series to increase the resolution of the conversion system.
A series connection of two CA3304s may be used to pro-
duce a 5-bit, 25MHz converter. Operation of two CA3304s in
parallel doubles the conversion speed (i.e., increases the
sampling rate from 25MHz to 50MHz). A data change pin
indicates when the present output differs from the previous,
thus allowing compaction of data storage.
Sixteen paralleled auto-balanced voltage comparators mea-
sure the input voltage with respect to a known reference to
produce the parallel-bit outputs in the CA3304. Fifteen com-
parators are required to quantize all input voltage levels in this
4-bit converter, and the additional comparator is required for
the overflow bit.
TEMP. RANGE (
16
15
14
13
12
11
10
9
-55 to 125
-55 to 125
-40 to 85
-40 to 85
-40 to 85
-40 to 85
V
CLK
V
V
V
V
V
CE1
AA
AA
DD
REF
REF
IN
-
+
-
+
o
C)
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC (W)
16 Ld SOIC (W)
16 Ld SBDIP
16 Ld SBDIP
Flash A/D Converters
PACKAGE
4-Bit, 25 MSPS,
File Number
E16.3
E16.3
M16.3
M16.3
D16.3
D16.3
PKG. NO.
1790.2

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ca3304 Summary of contents

Page 1

... The overflow bit makes possible the connection of two or more CA3304s in series to increase the resolution of the conversion system. A series connection of two CA3304s may be used to pro- duce a 5-bit, 25MHz converter. Operation of two CA3304s in parallel doubles the conversion speed (i.e., increases the sampling rate from 25MHz to 50MHz) ...

Page 2

... Voltage Range . . . . . . . V AA Operating Temperature CA3304D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 CA3304E, CA3304M -40 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ...

Page 3

... Input current is due to energy transferred to the input at the start of the sample period. The average value is dependent on input and V DD voltage. 3. The CLK input is a CMOS inverter with a 50k feedback resistor. It operates from the V with a 1V minimum source. P-P 4. Parameter not tested, but guaranteed by design or characterization. CA3304, CA3304A 2V 5V ...

Page 4

... NOTE: 1. The voltages listed are the ideal centers of each output code shown as a function of its associated reference voltage See Ideal Transfer Curve Figure 6. The output code should exist for an input equal to the ideal center voltage CA3304, CA3304A Bit 1 (LSB). Bit 2. Bit 3. ...

Page 5

... NOTE: CE1 and CE2 inputs and data outputs have standard CMOS protection networks to V standard CMOS protection networks Timing Diagrams DATA SHIFTED INTO OUTPUT REGISTERS AUTO 1 BALANCE CLOCK B4, DC & CE1 CE2 BITS 1-4 DC, OF CA3304, CA3304A 2 OUTPUT REGISTER COUNT LATCH ...

Page 6

... With 2 as standby state (indefinite standby, lower power than 3B) Typical Performance Curves -50 - TEMPERATURE ( FIGURE 4. DATA DELAY vs TEMPERATURE CA3304, CA3304A 2 CLOCK NEW DATA OUTPUT With 1 as standby state (indefinite standby, double pulse needed) SAMPLE ENDS OLD DATA INVALID DATA FIGURE 3C ...

Page 7

... TEMPERATURE ( FIGURE 6. NON-LINEARITY vs TEMPERATURE 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0. (MHz) S FIGURE 8. NON-LINEARITY vs SAMPLE FREQUENCY 4.00 3.80 3.60 3.40 3.20 3.00 2.80 2.60 2.40 2.20 2. (MHz) I FIGURE 10. EFFECTIVE BITS vs INPUT FREQUENCY CA3304, CA3304A (Continued) 0.10 0.09 0.08 0.07 INL 0.06 0.05 DNL 0.04 0.03 0.02 0.01 0. FIGURE 7. NON-LINEARITY vs REFERENCE VOLTAGE 4.00 3.80 3.60 3.40 INL 3.20 3.00 2.80 2.60 2.40 2.20 DNL 2. -40 -30 FIGURE 9. EFFECTIVE BITS vs TEMPERATURE 7 ...

Page 8

... Typical Performance Curves 2V REFERENCE REMOTE 2V INTO 50 SOURCE FIGURE 12A. TYPICAL CA3304 UNIPOLAR CIRCUIT CONFIGURATION +1V REFERENCE REMOTE 1V INTO 50 SOURCE ANALOG GROUND FIGURE 12B. TYPICAL CA3304 BIPOLAR CIRCUIT CONFIGURATION CA3304, CA3304A (Continued) 27 CA3304 0.1 F CE2 4.7 F TAN CER V + REF + 0.1 F 4.7 F TAN CER DC, OF, ...

Page 9

... The conversion process now takes 60ns. [Note that the above numbers do not include the t Increased Accuracy In most case the accuracy of the CA3304 should be sufficient without any adjustments. In applications where accuracy is of utmost importance, two adjustments can be made to obtain better accuracy; i.e., offset trim and gain trim. ...

Page 10

... If the supply is noisy, decouple V + with a resistor as shown in Figure 12A. AA The CA3304 outputs current spikes to its input at the start of the auto-balance and sample clock phases. A low impedance source, such as a locally-terminated 50 cable, should be used to drive the input terminal. A fast- settling buffer such as the HA-5033, HA-5242, or CA3450 should be used if the source is high impedance ...

Page 11

... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com CA3304, CA3304A +FULL SCALE REF. BUFFER INPUT FIGURE 13. TYPICAL CA3304 5-BIT CONFIGURATION OVERFLOW ...

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