x79002 Intersil Corporation, x79002 Datasheet
x79002
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x79002 Summary of contents
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... SCK Control Logic X79000, X79001, X79002 March 17, 2005 DESCRIPTION The X79000 is a family of Single Channel Non-Volatile (NV) Digital-to-Analog Converters with integrated voltage reference, configurable output buffer, general purpose EEPROM, and selectable full scale and zero offset voltages. The X79000 series implements an SPI serial bus interface with slave address identification allowing devices on some options ...
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... X79001 / X79002 FUNCTIONAL DIAGRAM Vcc Vss VH VL Variable Gain Voltage & Level Shift Reference Variable Gain Power-up & Level Shift RDY Logic A[5:0] General Serial Purpose SCK Interface EEPROM and SO Control Logic SI DAC Initial CS Value Register X79001 PIN CONFIGURATION TSSOP SCK 1 20 ...
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... Unbuffered DAC Output Pin. Vbuf Buffered DAC Output Pin. VFB Feedback Pin for Buffer Stage. Vref Bandgap Voltage Output Pin. VH Full Scale Voltage Input or Output Pin. VL Zero Scale Voltage Input or Output Pin. DNC Do Not Connect 3 X79000, X79001, X79002 Pin Description FN8147.0 March 17, 2005 ...
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... Digital feed through Output load regulation Short circuit current @ Vbuf Capacitive Loading Stability 4 X79000, X79001, X79002 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or an other conditions above those listed in the operational sections of this specification) is not implied ...
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... A2 input High voltage V CS, SI, SCK, CLR, OE, UP and HYST DOWN input hysteresis Power Requirements Iccstby Standby current into Vcc pin Iccfull Full operation current into Vcc pin Iccwrite Nonvolatile Write current into Vcc pin 5 X79000, X79001, X79002 Min Typ Max Unit 1.20 1.21 1.22 50 ppm ...
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... High May change Will change from High to from High to Low Low Don’t Care: Changing: Changes State Not Allowed Known N/A Center Line is High Impedance 6 X79000, X79001, X79002 Min Typ 1.5 2.6 100 VH0 VL2 VL1 3.025V and V = 0.151V INL varies inversely with the range of (V ...
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... UP or DOWN rise or fall times UDRF DEVICE ADDRESS PINS TIMING CS A0–A5 ADDRESS PINS TIMING Symbol Parameter t A0, A1, A2, A3, A4, A5 setup time ASU t A0, A1, A2, A3, A4, A5 hold time AHO 7 X79000, X79001, X79002 t UDH t UDL t t UDDIST t UDDIST UDH t UDL Parameter (Any Instruction) ...
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... CS after a valid nonvolatile write sequence, to the end of the self-timed internal non-volatile write WC cycle the minimum cycle time to be allowed for any non-volatile write cycle by the user, unless the “WIP” bit is used to check for the end of the write cycle. 8 X79000, X79001, X79002 t CYC ... t ...
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... Output Valid from Clock Low V t Output Hold Time HO (1) t Output Rise Time RO (1) t Output Fall Time FO Note: 1. These parameters are periodically sampled and not 100% tested. 9 X79000, X79001, X79002 t t CYC ... t HO ... Min. 200 LAG t DIS LSB Max ...
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... DAC can have an output range (4.75 - 0.150V) = 4.60V. The buffer would need a gain >1 set by adding feedback resistors to the V pins, depending on the V Value For applications requiring voltages greater than 5V external Intersil recommends the X79002 plus an external buffer 151mV 1 0 605mV UP/DOWN Operation ...
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... Decrement 1000 0111 1110 Decrement 11 X79000, X79001, X79002 A HIGH to LOW transition on the UP pin, while the DOWN pin is LOW, increments the selected binary word by one. A HIGH to LOW transition on the DOWN pin, while the UP pin is LOW, decrements the selected binary word by one. ...
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... General Purpose Memory (GPM) – Control and Status Registers The GPM is all nonvolatile EEPROM, located at memory addresses 00h to 37h. 12 X79000, X79001, X79002 Figure 2. X79000 Memory Map Address 3Fh 38h 37h 00h ...
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... When the R/W bit is “1”, then a Read operation is selected. A “0” selects a write operation. If the value of the Device Address bits doesn’t match the logic levels at the Address pins, then the Read or Write operation is aborted. 13 X79000, X79001, X79002 DAC9 ...
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... The page address remains constant during a single write operation. 14 X79000, X79001, X79002 For example, if the Write operation includes 6 Data Bytes, and the Memory Address byte is 5 (decimal), the first 3 bytes are written to locations 5, 6, and 7, while the last 3 bytes are written to locations 0, 1, and 2 ...
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... WRITE STATUS POLLING COMMAND CS Device Address Signal High Impedance Signal at SO For every byte, the MSB is transmitted first and the LSB is sent last. 15 X79000, X79001, X79002 Memory Address Byte 1 X First Read Data Byte Memory First Data Address Byte Byte to Write 0 ...
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... Vbuf output. 16 X79000, X79001, X79002 Using the VH and VL pins for multiplying functions When a time-varying waveform is applied at either reference input pin, the output reflects a scaled version of that waveform (see Figure 5) ...
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... Variable Gain & Level Shift *Set Register 3Ch for FIGURE 5. MULTIPLYING DAC CONFIGURATION – Variable Gain & Level Shift Variable Gain & Level Shift 17 X79000, X79001, X79002 X79000 DAC + Core – X79000 DAC + Core – = 2.42V = 0.605V VH X79000 DAC + Core – ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 X79000, X79001, X79002 20-LEAD PLASTIC, TSSOP PACKAGE TYPE V .025 (.65) BSC .169 (4.3) ...