xa2c32a Xilinx Corp., xa2c32a Datasheet - Page 10

• Manufacturer Part Number: xa2c32a
• Description: Coolrunner-ii Automotive Cpld Product Family
• Manufacturer: Xilinx Corp.

CoolRunner-II Automotive CPLD Product Family
Programming
The programming data sequence is delivered to the device
using either Xilinx iMPACT software and a Xilinx download
cable, a third-party JTAG development system, a
JTAG-compatible board tester, or a simple microprocessor
interface that emulates the JTAG instruction sequence. The
iMPACT software also outputs serial vector format (SVF)
files for use with any tools that accept SVF format, including
automatic test equipment. CoolRunner-II Automotive CPLD
devices must be programmed at temperatures of T
to +70° C only.See
more information on how to program.
In System Programming
All CoolRunner-II Automotive CPLD parts are 1.8V in sys-
tem programmable. This means they derive their program-
ming voltage and currents from the 1.8V V
supply voltage) pins on the part. The V
ticipate in this operation, as they may assume another volt-
age ranging as high as 3.3V down to 1.5V. A 1.8V V
required to properly operate the internal state machines and
charge pumps that reside within the CPLD to do the nonvol-
atile programming operations. The JTAG interface buffers
are powered by a dedicated power pin, V
independent of all other supply pins. V
nected. Xilinx software is provided to deliver the bit-stream
to the CPLD and drive the appropriate IEEE 1532 protocol.
To that end, there is a set of IEEE 1532 commands that are
supported in the CoolRunner-II Automotive CPLD parts.
Programming times are less than one second for 32 to 256
macrocell parts. Programming times are less than four sec-
onds for 384 macrocell part. Programming of CoolRunner-II
Automotive CPLDs is only guaranteed when operating in
the commercial temperature and voltage ranges as defined
in the device-specific data sheets.
JTAG Instructions
Table 6
same commands may be used by third party ATE products,
as well. The internal controllers can operate as fast as
66 MHz.
Table 6: JTAG Instructions
10
00000000
00000011
11111111
00000010
Code
shows the commands available to users. These
Instruction
PRELOAD
EXTEST
BYPASS
INTEST
CoolRunner-II Application Notes
Force boundary scan data onto
outputs
Latch macrocell data into
boundary scan cells
Insert bypass register between
TDI and TDO
Force boundary scan data onto
inputs and feedbacks
Description
CCIO
CCAUX
CCAUX
pins do not par-
must be con-
CC
, which is
A
(internal
= 0° C
www.xilinx.com
CC
for
is
Table 6: JTAG Instructions
Power-Up Characteristics
CoolRunner-II Automotive CPLD parts must operate under
the demands of both the high-speed and the portable mar-
ket places, therefore, they must support hot plugging for the
high-speed world and tolerate most any power sequence to
its various voltage pins. They must also not draw excessive
current during power-up initialization. To those ends, the
general behavior is summarized as follows:
1. I/O pins are disabled until the end of power-up.
2. As supply rises, configuration bits transfer from
3. As power up completes, the I/Os become configured.
4. For specific configuration times and power up
CoolRunner-II Automotive CPLD I/O pins are well behaved
under all operating conditions. During power-up, CoolRun-
ner-II devices employ internal circuitry which keeps the
devices in the quiescent state until the V
age is at a safe level (approximately 1.3V). In the quiescent
state, JTAG pins are disabled, and all device outputs are
disabled with the pins weakly pulled high, as shown in
8. When the supply voltage reaches a safe level, all user
registers become initialized, and the device is immediately
available for operation, as shown in
are obtained with a monotonic V
If the device is in the erased state (before any user pattern
is programmed), the device outputs remain disabled with a
weak pull-up. The JTAG pins are enabled to allow the
device to be programmed at any time. All devices are
shipped in the erased state from the factory.
Applying power to a blank part may result in a higher current
flow as the part initializes. This behavior is normal and may
persist for approximately 2 seconds, depending on the
power supply ramp.
If the device is programmed, the device inputs and outputs
take on their configured states for normal operation. The
JTAG pins are enabled to allow device erasure or bound-
ary-scan tests at any time.
00000001
11111101 USERCODE Read USERCODE
11111100
11111010
Code
nonvolatile memory to SRAM cells.
requirements, see the device specific data sheet.
Instruction
IDCODE
CLAMP
HIGHZ
Read IDCODE
Force output into high
impedance state
Latch present output state
DS315 (v1.1) October 31, 2006
CC
rise in less than 1 ms).
Figure 12
Description
Product Specification
CCINT
(best results
supply volt-
Table
R