xa2c32a Xilinx Corp., xa2c32a Datasheet - Page 9

• Manufacturer Part Number: xa2c32a
• Description: Coolrunner-ii Automotive Cpld Product Family
• Manufacturer: Xilinx Corp.

Timing Model
Figure 10
represents one aspect of the overall architecture from a tim-
ing viewpoint. Each little block is a time delay that a signal
will incur if the signal passes through such a resource. Tim-
ing reports are created by tallying the incremental signal
delays as signals progress within the CPLD. Software cre-
ates the timing reports after a design has been mapped
Table 5: Timing Parameter Definitions
DS315 (v1.1) October 31, 2006
Product Specification
Buffer Delays
T
T
T
T
T
T
T
T
P-term Delays
T
T
T
OUT
Symbol
lN
DIN
GCK
GSR
GTS
EN
SLEW
CT
LOGI1
LOGI2
Note: Always refer to the timing report in ISE Software for accurate timing values for paths.
shows the CoolRunner-II CPLD timing model. It
T
T
T
T
R
T
GCK
GSR
GTS
DIN
IN
Input Buffer Delay
Direct data register input delay
Global clock (GCK) buffer delay
Global set/reset (GSR) buffer delay
Global output enable (GTS) buffer delay
Output buffer delay
Output buffer enable/disable delay
Output buffer slew rate control delay
Control Term delay (single PT or FB-CT)
Single P-term logic delay
Multiple P-term logic delay adder
T
T
T
T
T
HYS
HYS
HYS
HYS
HYS
Figure 10: CoolRunner-II Automotive CPLD Timing Model
Parameter
T
T
CT
LOGI1
T
LOGI2
www.xilinx.com
onto the specific part, and knows the specific delay values
for a given speed grade. Equations for the higher level tim-
ing values (i.e., T
summarizes the individual parameters and provides a brief
definition of their associated functions. Xilinx application
note
family timing with several examples.
Table 5: Timing Parameter Definitions (Continued)
D/T
CE
Macrocell Delays
T
T
T
T
T
T
T
T
Feedback Delays
T
T
S/R
AOI
Symbol
PDI
SUI
HI
ECSU
ECHO
COI
HYS
F
OEM
T
SUI
XAPP375
T
T
PDI
T
T
T
F
CoolRunner-II Automotive CPLD Product Family
ECSU
ECHO
AOI
T
T
COI
HI
Macro cell input to output valid
Macro register setup before clock
Macro register hold after clock
Macro register enable clock setup time
Macro register enable clock hold time
Macro register clock to output valid
Macro register set/reset to output valid
Hysteresis selection delay adder
Feedback delay
Macrocell to Global OE delay
details the CoolRunner-II Automotive CPLD
PD
and F
T
OUT
T
SYSTEM
OEM
Parameter
) are available.
T
EN
XAPP375_03_010303
T
SLEW
Table 5
9