adsp-21992 Analog Devices, Inc., adsp-21992 Datasheet - Page 10

• Manufacturer Part Number: adsp-21992
• Description: Mixed Signal Dsp Controller With Can
• Manufacturer: Analog Devices, Inc.

ADSP-21992
PWM GENERATION UNIT
Key features of the 3-phase PWM generation unit are:
The ADSP-21992 integrates a flexible and programmable, 3-
phase PWM waveform generator that can be programmed to
generate the required switching patterns to drive a 3-phase volt-
age source inverter for ac induction (ACIM) or permanent
magnet synchronous (PMSM) motor control. In addition, the
PWM block contains special functions that considerably sim-
plify the generation of the required PWM switching patterns for
control of the electronically commutated motor (ECM) or
brushless dc motor (BDCM). Tying a dedicated pin, PWMSR,
to GND, enables a special mode, for switched reluctance
motors (SRM).
The six PWM output signals consist of three high side drive pins
(AH, BH, and CH) and three low side drive signals pins (AL, BL,
and CL). The polarity of the generated PWM signals may be set
via hardware by the PWMPOL input pin, so that either active
HI or active LO PWM patterns can be produced.
The switching frequency of the generated PWM patterns is pro-
grammable using the 16-bit PWMTM register. The PWM
generator is capable of operating in two distinct modes, single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period,
so that the resultant PWM patterns are symmetrical about the
midpoint of the PWM period. In the double update mode, a sec-
ond updating of the PWM registers is implemented at the
midpoint of the PWM period. In this mode, it is possible to pro-
duce asymmetrical PWM patterns that produce lower harmonic
distortion in 3-phase PWM inverters.
AUXILIARY PWM GENERATION UNIT
Key features of the auxiliary PWM generation unit are:
• 16-bit, center-based PWM generation unit.
• Programmable PWM pulse width, with resolutions to
• Single/double update modes
• Programmable dead time and switching frequency.
• Twos complement implementation which permits smooth
• Possibility to synchronize the PWM generation to an exter-
• Special provisions for BDCM operation (crossover and
• Wide variety of special switched reluctance (SR)
• Output polarity and clock gating control.
• Dedicated asynchronous PWM shutdown signal.
• Multiple shutdown sources, independently for each unit.
• 16-bit, programmable frequency, programmable duty cycle
• Independent or offset operating modes.
• Double buffered control of duty cycle and period registers.
12.5 ns (at 80 MHz HCLK Rate).
transition into full ON and full OFF states.
nal synchronization.
output enable functions).
operating modes.
PWM outputs.
Rev. A | Page 10 of 60 | August 2007
The ADSP-21992 integrates a 2-channel, 16-bit, auxiliary PWM
output unit that can be programmed with variable frequency,
variable duty cycle values and may operate in two different
modes, independent mode or offset mode. In independent
mode, the two auxiliary PWM generators are completely inde-
pendent and separate switching frequencies and duty cycles may
be programmed for each auxiliary PWM output. In offset mode
the switching frequency of the two signals on the AUX0 and
AUX1 pins is identical. Bit 4 of the AUXCTRL register places
the auxiliary PWM channel pair in independent or offset mode.
The auxiliary PWM generation unit provides two chip output
pins, AUX0 and AUX1 (on which the switching signals appear),
and one chip input pin, AUXTRIP, which can be used to shut
down the switching signals—for example, in a fault condition.
ENCODER INTERFACE UNIT
The ADSP-21992 incorporates a powerful encoder interface
block to incremental shaft encoders that are often used for posi-
tion feedback in high performance motion control systems.
The encoder interface unit (EIU) includes a 32-bit quadrature
up-/downconverter, programmable input noise filtering of the
encoder input signals and the zero markers, and has four dedi-
cated chip pins. The quadrature encoder signals are applied at
the EIA and EIB pins. Alternatively, a frequency and direction
set of inputs may be applied to the EIA and EIB pins. In addi-
tion, two north marker/strobe inputs are provided on pins EIZ
and EIS. These inputs may be used to latch the contents of the
encoder quadrature counter into dedicated registers,
EIZLATCH and EISLATCH, on the occurrence of external
events at the EIZ and EIS pins. These events may be pro-
grammed to be either rising edge only (latch event) or rising
edge if the encoder is moving in the forward direction and fall-
ing edge if the encoder is moving in the reverse direction
(software latched north marker functionality).
• Separate auxiliary PWM synchronization signal and associ-
• Separate auxiliary PWM shutdown signal (AUXTRIP).
• Quadrature rates to 53 MHz (at 80 MHz HCLK rate).
• Programmable filtering of all encoder input signals.
• 32-bit encoder counter.
• Variety of hardware and software reset modes.
• Two registration inputs to latch EIU count value with cor-
• Status of A/B signals latched with reading of EIU
• Alternative frequency and direction mode.
• Single north marker mode.
• Count error monitor function with dedicated error
• Dedicated 16-bit loop timer with dedicated interrupt.
• Companion encoder event (1⁄T) timer unit.
ated interrupt (can be used to trigger ADC convert start).
responding registration interrupt.
count value.
interrupt.