adsp-21992 Analog Devices, Inc., adsp-21992 Datasheet - Page 13

• Manufacturer Part Number: adsp-21992
• Description: Mixed Signal Dsp Controller With Can
• Manufacturer: Analog Devices, Inc.

configuration of the PD, STCK, and STALL bits in the PLLCTL
register to select between the low power modes as the DSP exe-
cutes the IDLE instruction. Depending on the mode, an IDLE
shuts off clocks to different parts of the DSP in the different
modes. The low power modes are:
Idle Mode
When the ADSP-21992 is in idle mode, the DSP core stops exe-
cuting instructions, retains the contents of the instruction
pipeline, and waits for an interrupt. The core clock and periph-
eral clock continue running.
To enter idle mode, the DSP can execute the IDLE instruction
anywhere in code. To exit idle mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions.
Power-Down Core Mode
When the ADSP-21992 is in power-down core mode, the DSP
core clock is off, but the DSP retains the contents of the pipeline
and keeps the PLL running. The peripheral bus keeps running,
letting the peripherals receive data.
To exit power-down core mode, the DSP responds to an inter-
rupt and (after two cycles of latency) resumes executing
instructions.
Power-Down Core/Peripherals Mode
When the ADSP-21992 is in power-down core/peripherals
mode, the DSP core clock and peripheral bus clock are off, but
the DSP keeps the PLL running. The DSP does not retain the
contents of the instruction pipeline. The peripheral bus is
stopped, so the peripherals cannot receive data.
To exit power-down core/peripherals mode, the DSP responds
to an interrupt and (after five to six cycles of latency) resumes
executing instructions.
Power-Down All Mode
When the ADSP-21992 is in power-down all mode, the DSP
core clock, the peripheral clock, and the PLL are all stopped.
The DSP does not retain the contents of the instruction pipe-
line. The peripheral bus is stopped, so the peripherals cannot
receive data.
To exit power-down core/peripherals mode, the DSP responds
to an interrupt and (after 500 cycles to restabilize the PLL)
resumes executing instructions.
CLOCK SIGNALS
The ADSP-21992 can be clocked by a crystal oscillator or a buff-
ered, shaped clock derived from an external clock oscillator. If a
crystal oscillator is used, the crystal should be connected across
the CLKIN and XTAL pins, with two capacitors connected as
shown in
• Idle
• Power-down core
• Power-down core/peripherals
• Power-down all
Figure
6. Capacitor values are dependent on crystal
Rev. A | Page 13 of 60 | August 2007
type and should be specified by the crystal manufacturer. A par-
allel resonant, fundamental frequency, microprocessor grade
crystal should be used for this configuration.
If a buffered, shaped clock is used, this external clock connects
to the DSP CLKIN pin. CLKIN input cannot be halted, changed,
or operated below the specified frequency during normal opera-
tion. This clock signal should be a TTL-compatible signal.
When an external clock is used, the XTAL input must be left
unconnected.
The DSP provides a user-programmable 1
tion of the input clock, including some fractional values, to
support 128 external to internal (DSP core) clock ratios. The
BYPASS pin, and MSEL6–0 and DF bits, in the PLL configura-
tion register, decide the PLL multiplication factor at reset. At
runtime, the multiplication factor can be controlled in software.
To support input clocks greater that 100 MHz, the PLL uses an
additional bit (DF). If the input clock is greater than 100 MHz,
DF must be set. If the input clock is less than 100 MHz, DF must
be cleared. For clock multiplier settings, see the ADSP-2199x
DSP Hardware Reference Manual.
The peripheral clock is supplied to the CLKOUT pin.
All on-chip peripherals for the ADSP-21992 operate at the rate
set by the peripheral clock. The peripheral clock (HCLK) is
either equal to the core clock rate or one half the DSP core clock
rate (CCLK). This selection is controlled by the IOSEL bit in the
PLLCTL register. The maximum core clock is 160 MHz for the
ADSP-21992BST, 150 MHz for both the ADSP-21992BBC and
ADSP-21992YBC, and 100 MHz for the ADSP-21992YST. The
maximum peripheral clock is 80 MHz for the ADSP-21992BST,
75 MHz for both the ADSP-21992BBC and ADSP-21992YBC,
and 50 MHz for the ADSP-21992YST—the combination of the
input clock and core/peripheral clock ratios may not exceed
these limits.
RESET AND POWER-ON RESET (POR)
The RESET pin initiates a complete hardware reset of the
ADSP-21992 when pulled low. The RESET signal must be
asserted when the device is powered up to assure proper initial-
ization. The ADSP-21992 contains an integrated power-on reset
(POR) circuit that provides an output reset signal, POR, from
the ADSP-21992 on power-up and if the power supply voltage
falls below the threshold level. The ADSP-21992 may be reset
Figure 6. External Crystal Connections
CLKIN
ADSP-2199x
XTAL
ADSP-21992
to 32
multiplica-