adsp-21992 Analog Devices, Inc., adsp-21992 Datasheet - Page 7

• Manufacturer Part Number: adsp-21992
• Description: Mixed Signal Dsp Controller With Can
• Manufacturer: Analog Devices, Inc.

The ADSP-21992 will halt program execution if the bus is
granted to an external device and an instruction fetch or data
read/write request is made to external general-purpose or
peripheral memory spaces. If an instruction requires two exter-
nal memory read accesses, the bus will not be granted between
the two accesses. If an instruction requires an external memory
read and an external memory write access, the bus may be
granted between the two accesses. The external memory inter-
face can be configured so that the core will have exclusive use of
the interface. DMA and bus requests will be granted. When the
external device releases BR, the DSP releases BG and continues
program execution from the point at which it stopped.
The bus request feature operates at all times, even while the DSP
is booting and RESET is active.
The ADSP-21992 asserts the BGH pin when it is ready to start
another external port access, but is held off because the bus was
previously granted. This mechanism can be extended to define
more complex arbitration protocols for implementing more
elaborate multimaster systems.
DMA CONTROLLER
The ADSP-21992 has a DMA controller that supports auto-
mated data transfers with minimal overhead for the DSP core.
Cycle stealing DMA transfers can occur between the
ADSP-21992 internal memory and any of its DMA capable
peripherals. Additionally, DMA transfers can be accomplished
between any of the DMA capable peripherals and external
devices connected to the external memory interface. DMA
capable peripherals include the SPORT and SPI ports, and ADC
control module. Each individual DMA capable peripheral has a
dedicated DMA channel. To describe each DMA sequence, the
DMA controller uses a set of parameters—called a DMA
descriptor. When successive DMA sequences are needed, these
DMA descriptors can be linked or chained together, so the com-
pletion of one DMA sequence autoinitiates and starts the next
sequence. DMA sequences do not contend for bus access with
the DSP core, instead DMAs “steal” cycles to access memory.
All DMA transfers use the DMA bus shown in
Page
tion for DMA bus access is needed. The arbitration for DMA
bus access appears in
Table 1. I/O Bus Arbitration Priority
DMA Bus Master
SPORT Receive DMA
SPORT Transmit DMA
ADC Control DMA
SPI Receive/Transmit DMA
Memory DMA
4. Because all of the peripherals use the same bus, arbitra-
Table
1.
Arbitration Priority
0—Highest
1
2
3
4—Lowest
Figure 2 on
Rev. A | Page 7 of 60 | August 2007
DSP PERIPHERALS ARCHITECTURE
The ADSP-21992 contains a number of special purpose, embed-
ded control peripherals, which can be seen in the functional
block diagram on Page 1. The ADSP-21992 contains a high per-
formance, 8-channel, 14-bit ADC system with dual-channel
simultaneous sampling ability across four pairs of inputs. An
internal precision voltage reference is also available as part of
the ADC system. In addition, a 3-phase, 16-bit, center-based
PWM generation unit can be used to produce high accuracy
PWM signals with minimal processor overhead. The
ADSP-21992 also contains a flexible incremental encoder inter-
face unit for position sensor feedback; two adjustable frequency
auxiliary PWM outputs, 16 lines of digital I/O; a 16-bit watch-
dog timer; three general-purpose timers, and an interrupt
controller that manages all peripheral interrupts. Finally, the
ADSP-21992 contains an integrated power-on-reset (POR) cir-
cuit that can be used to generate the required reset signal for
device power-on.
The ADSP-21992 has an external memory interface that is
shared by the DSP core, the DMA controller, and DMA capable
peripherals, which include the ADC, SPORT, and SPI commu-
nication ports. The external port consists of a 16-bit data bus, a
20-bit address bus, and control signals. The data bus is config-
urable to provide an 8- or 16-bit interface to external memory.
Support for word packing lets the DSP access 16- or 24-bit
words from external memory regardless of the external data
bus width.
The memory DMA controller lets the ADSP-21992 move data
and instructions from between memory spaces: internal-to-
external, internal-to-internal, and external-to-external. On-chip
peripherals can also use this controller for DMA transfers.
The embedded SHARC core can respond to up to 17 interrupts
at any given time: three internal (stack, emulator kernel, and
power-down), two external (emulator and reset), and 12 user-
defined (peripherals) interrupts. Programmers assign each of
the 32 peripheral interrupt requests to one of the 12 user-
defined interrupts. These assignments determine the priority of
each peripheral for interrupt service.
The following sections provide a functional overview of the
ADSP-21992 peripherals.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
The serial peripheral interface (SPI) port provides functionality
for a generic configurable serial port interface based on the SPI
standard, which enables the DSP to communicate with multiple
SPI-compatible devices. Key features of the SPI port are:
• Interface to host microcontroller or serial EEPROM.
• Master or slave operation (3-wire interface MISO, MOSI,
• Data rates to HCLK
• 8- or 16-bit transfer.
• Programmable clock phase and polarity.
• Broadcast Mode–1 master, multiple slaves.
• DMA capability and dedicated interrupts.
SCK).
4 (16-bit baud rate selector).
ADSP-21992