saa7392 NXP Semiconductors, saa7392 Datasheet - Page 22

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saa7392

Manufacturer Part Number
saa7392
Description
Channel Encoder/decoder Cdr60
Manufacturer
NXP Semiconductors
Datasheet

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7.5.3
The behaviour of this register is dependent upon whether its being read or written. The behaviour for the write operation
is described in Tables 24 to 27. When read the 8 MSBs of the PLL frequency counter are returned; this is described in
Tables 24 and 28.
Table 24 PLL Lock Select Register (address 00H) - WRITE/READ
Table 25 Description of PLLLock bits for write operation
Table 26 Selection of phase override setting
Table 27 Selection of PLL lock
2000 Mar 21
PLLForceL.3 PLLForceL.2 PLLForceL.1 PLLForceL.0
PhaOset.2
PLLFreq.7
LockOride
Channel encoder/decoder CDR60
BIT
7
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
1
X
0
0
0
0
1
PLL L
OCK
PLLForceL.3 These 4 bits are used to select the PLL lock; see Table 27.
PLLForceL.2
PLLForceL.1
PLLForceL.0
PhaOset.1
PhaOset.2
PhaOset.2
PhaOset.1
PhaOset.0
PLLFreq.6
LockOride
SYMBOL
S
ELECT
6
0
0
1
1
0
0
1
1
X
0
0
1
1
0
R
EGISTER
When LockOride = 0, then automatic lock behaviour selected, PLLForceL<3:0> must be
set to ‘0000’. When LockOride = 1, then PLL manual override, PLLForceL<3:0> must
also be programmed.
These 3 bits are used to select the phase override settings; see Table 26.
PhaOset.0
PhaOset.1
PLLFreq.5
5
0
1
0
1
0
1
0
1
(PLLL
X
0
0
0
1
0
OCK
reserved
3
2
1
correct equalisation
1
2
3
/
/
/
/
/
/
PhaOset.0
PLLFreq.4
8
8
8
8
8
8
)
PLL clock over-equalized T3
PLL clock over-equalized T3
PLL clock over-equalized T3
PLL clock under-equalized T3
PLL clock under-equalized T3
PLL clock under-equalized T3
4
X
0
1
0
0
0
22
PLLForceL.3 PLLForceL.2 PLLForceL.1 PLLForceL.0
PLLFreq.3
automatic lock behaviour
force PLL in-lock
force PLL into outer-lock
force PLL into inner-lock
force PLL into Hold mode (PLL frequency can be
forced using preset value in register PLLFreq)
all other combinations are reserved
3
DESCRIPTION
PHASE OVERRIDE
PLLFreq.2
2
PLL LOCK
PLLFreq.1
Preliminary specification
1
SAA7392
PLLFreq.0
0

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