ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 128

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
The Multiply-Accumulator decodes its I/O addresses from ADDR[7:0]. In addition,
it monitors ADDR[15:8] to detect the final transfer of a block using the OTI2R or
INI2R instructions. These instructions drive the value in the CPU’s B register onto
ADDR[15:8] and the value in the CPU’s C register onto ADDR[7:0]. The B register
decrements after completion of each transfer in the OTI2R or INI2R block transfer.
The C register increments after completion of each transfer. The final transfer
occurs when B contains the value of
0 and the block instruction terminates. Refer to the eZ80
more information on these CPU instructions and CPU registers.
Defining A New Calculation As READY
When writing a new calculation to the MACC control registers, any of the following
actions change the state of the DATA bank from EMPTY to READY:
•
•
•
If the MACC is prepared to begin a new calculation (CALC bank status is EMPTY
or DONE), the banks are immediately swapped as soon as the new calculation
defined in the DATA bank is READY. When this swap occurs, the CALC bank sta-
tus becomes IN PROGRESS.
Defining The DATA Bank As EMPTY
Defining the DATA Bank as EMPTY indicates completion of a result read opera-
tion. When reading a result from the MACC Accumulator registers, any of the fol-
lowing actions change the state of the DATA bank from DONE to EMPTY:
•
•
Alternatively, any write operation to any of the MACC registers besides
MACC_STAT also changes the DATA bank status from DONE to EMPTY. This
state change occurs because write operations generally indicate a requirement to
define a new calculation.
A write to MACC_AC4, the most significant byte of the MACC Accumulator.
A write to MACC_CTL with ADDR[15:8] =
this write requirement during its final transfer)
–
A write to MACC_AC0, MACC_AC1, MACC_AC2, or MACC_AC3 with
ADDR[15:8] =
its final transfer)
A read from MACC_AC4, the most significant byte of the MACC Accumulator
A read from MACC_AC0, MACC_AC1, MACC_AC2, or MACC_AC3 with
ADDR[15:8] =
This write also clears the MACC Accumulator
01h
01h
, as in the final transfer, using an INI2R instruction
(an OTI2R instruction satisfies this write requirement during
PRELIMINARY
01h
. After this final transfer, B decrements to
01h
eZ80190 Product Specification
(an OTI2R instruction satisfies
®
CPU User Manual for
Multiply-Accumulator
114