ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 84

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

eZ80190 Product Specification
70
the application writes the transmit data bytes to the UARTx_THR register. The
number of bytes that the application writes depends on whether or not the FIFO is
enabled. If the FIFO is enabled, the application can write 16 bytes at one time. If
the FIFO is not enabled, the application can Write Only one byte at a time. As a
result of the first write, the interrupt is deactivated. The processor then waits for
the next interrupt. When the interrupt is raised by the UART module, the proces-
sor repeats the same process until it exhausts all of the data for transmission.
To control and check the modem status, the application sets up the modem by
writing to UARTx_MCTL register and reading from the UARTx_MSR register
before starting the above process.
Receive. The receiver is always enabled and continually checks for the start bit
on the RXD input signal. When an interrupt is raised by the UART module, the
application reads the UARTx_IIR register and determines the cause of the inter-
rupt. If the cause is a line status interrupt, the application reads the UARTx_LSR
register, reads the data byte, then discards the byte or takes other action. If the
interrupt is caused by a RECEIVE DATA READY condition, the application alter-
nately reads the UARTx_LSR and UARTx_RBR registers and removes all
received data bytes. It reads the UARTx_LSR register before reading the
UARTx_RBR register to determine if there is a NO ERROR condition in the
received data.
To control and check modem status, the application sets up the modem by writing
to the UARTx_MCTL register and reading the UARTx_MSR register before start-
ing the above process.
Poll Mode Transfers
When interrupts are disabled, all data transfers are referred to as poll mode trans-
fers. In poll mode transfers, the application must continually poll the UARTx_LSR
register to transmit or receive data without enabling the interrupts. This condition
is also true for the UARTx_MSR register. If the interrupts are not enabled, the data
in the UARTx_IIR register cannot be used to determine the cause of an interrupt.
UART Registers
After a system reset, all UART registers are set to their default values. Any writes
to unused registers or register bits are ignored. READs return a value of 0. For
compatibility with future versions of this part, unused bits within a register should
always be written with a value of 0. READ/WRITE attributes, reset conditions, and
bit descriptions of all UART registers are provided in this section.
UART Transmit Holding Register
If less than eight bits are programmed for transmission, the lower bits of the byte
written to the UART Transmit Holding Register, indicated in
Table
26, are selected
PS006613-0306
PRELIMINARY
Universal Asynchronous Receiver/Transmitter