ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 93

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Bit
Position
3
FE
2
PE
1
OE
0
DR
Value
0
1
0
1
0
1
0
1
Description
No framing error is detected for the character at the top of the
FIFO. This bit is reset to 0 when the UARTx_LSR register is
read.
A framing error is detected for the character at the top of the
FIFO. This bit is set to 1 when the stop bit following the data/
parity bit is logic 0.
The received character at the top of the FIFO does not
produce a parity error. This bit is reset to 0 when the
UARTx_LSR register is read.
The received character at the top of the FIFO contains a parity
error.
The received character at the top of the FIFO does not
contain an overrun error. This bit is reset to 0 when the
UARTx_LSR register is read.
An overrun error is detected. If the FIFO is not enabled, this
error indicates the data in the receive buffer register was not
read before the next character was transferred into the
receiver buffer register. If the FIFO is enabled, this error
indicates the FIFO was already full when an additional
character was received by the receiver shift register. The
character in the receiver shift register is not placed into the
receive FIFO.
This bit is reset to 0 when the UARTx_RBR register is read or
when all bytes are read from the receive FIFO.
Data Ready
If the FIFO is not enabled, this bit is set to 1 when a complete
incoming character is transferred into the receiver buffer
register from the receiver shift register. If the FIFO is enabled,
this bit is set to 1 when a character is received and transferred
to the receive FIFO.
PRELIMINARY
Universal Asynchronous Receiver/Transmitter
eZ80190 Product Specification
79