ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 20

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Pin # Symbol
10
11
12
13
14
15
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued)
Function
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Signal Direction
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
PRELIMINARY
Description
The ADDR0 is configured as an output in normal
operation. The address bus selects a location in
memory or I/O space to be read or written. This
pin is configured as an input during bus
acknowledge cycles. Drives the Chip Select/Wait
State Generator block to generate Chip Selects.
The ADDR1 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
The ADDR2 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
The ADDR3 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
The ADDR4 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
The ADDR5 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
Architectural Overview
6