mc68hc908mr8 Freescale Semiconductor, Inc, mc68hc908mr8 Datasheet - Page 231

• Manufacturer Part Number: mc68hc908mr8
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

12.4.3.2 Buffered Output Compare
12.4.4 Pulse-Width Modulation (PWM)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
NOTE:
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the PTB5/TCH0B pin. The TIMB
channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIMB channel 0 status and control register
(TBSC0) links channel 0 and channel 1. The output compare value in the
TIMB channel 0 registers initially controls the output on the
PTB5/TCH0B pin. Writing to the TIMB channel 1 registers enables the
TIMB channel 1 registers to synchronously control the output after the
TIMB overflows. At each subsequent overflow, the TIMB channel
registers (0 or 1) that control the output are the ones written to last. TSC0
controls and monitors the buffered output compare function, and TIMB
channel 1 status and control register (TBSC1) is unused. While the
MS0B bit is set, the channel 1 pin, PTB6/TCH1B, is available as a
general-purpose input/output (I/O) pin.
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should
track the currently active channel to prevent writing a new value to the
active channel. Writing to the active channel registers is the same as
generating unbuffered output compares.
By using the toggle-on-overflow feature with an output compare channel,
the TIMB can generate a PWM signal. The value in the TIMB counter
modulo registers determines the period of the PWM signal. The channel
pin toggles when the counter reaches the value in the TIMB counter
modulo registers. The time between overflows is the period of the PWM
signal.
As
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIMB to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIMB to set the pin if the state of the PWM
pulse is logic 0.
Figure 12-3
Timer Interface B (TIMB)
shows, the output compare value in the TIMB channel
Timer Interface B (TIMB)
Functional Description
Technical Data
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