mc68hc912bd32 Freescale Semiconductor, Inc, mc68hc912bd32 Datasheet - Page 186

• Manufacturer Part Number: mc68hc912bd32
• Description: 16-bit Device Composed Of Standard On-chip Peripherals
• Manufacturer: Freescale Semiconductor, Inc

Error Handling
SYNC Pulse
Detection
Byteflight™ Module
MC68HC912BD32 Rev 1.0
Message Format Error
SYNC Pulse Too Early Error
SYNC Pulse Lost Error
Illegal Pulse Error
Error Type
The serial bus interface module detects and handles the following types
of errors:
The Rx pin of the serial bus interface module is internally connected to
its own Tx pin during Tx activity and for 8*t_bit after last Tx activity (to
avoid receiving of echoes).
A Sync Pulse is defined as a continuous dominant pulse with :
t_syn_a_min < t_syn_a < t_syn_a_max or
t_syn_n_min < t_syn_n < t_syn_n_max
Any dominant pulse within the wait times t_wx, t_w0 - t_syn_n_max is
considered as an error. If this pulse has a valid SYNC length the cycle is
restarted and a SYNC too early error is set. If the pulse has not a valid
length an illegal pulse error or a message format error is issued (see
Incorrect CRC, incorrect START bit or STOP bit
(Frame), missing or corrupted message start
sequence, bus-activity during the bus idle time
or before expiry of (t_cyc_min - t_syn_n) since
the last correct sync pulse: dominant pulse of
length t: t_start_seq < t < t_syn_a_min
A pulse has not the required position of an
ALARM or NORMAL pulse, the pulse appears
too early
No valid SYNC pulse detected until end of cycle
t_cyc_max
Before expiry of (t_cyc_min - t_syn_n) since the
last correct sync pulse: dominant pulse of length
t detected on the bus:
t_syn_a_max
or
t > t_syn_n_max
after expiry of (t_cyc_min - t_syn_n) since the
last correct sync pulse: all dominant pulses
which are not correct sync-normal or
sync-alarm pulses lead to this error
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 37 Error Handling
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Error Description
t t_syn_n_min
Byteflight™ Module
The node is still synchronized.
Transmission and reception is
possible after t_idle_min.
Set flag and generate interrupt if
enabled.
SYNC pulse is used for
synchronization. Set flag and
generate interrupt if enabled.
No transmission or reception
until the next correct SYNC
pulse. Set flag and generate
interrupt if enabled.
No transmission or reception
until the next correct SYNC
pulse.
Set flag and generate interrupt if
enabled.
Error Handling
16-sibus