mc68hc05jb4p Freescale Semiconductor, Inc, mc68hc05jb4p Datasheet
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... Freescale Semiconductor 68HC05JB4 68HC705JB4 © Freescale Semiconductor, Inc., 2004. All rights reserved. SPECIFICATION (General Release) February 24, 1999 Semiconductor Products Sector HC05JB4GRS/H REV 2 ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Section 1.1 FEATURES ...................................................................................................... 1-1 1.2 MASK OPTIONS.............................................................................................. 1-2 1.3 MCU STRUCTURE.......................................................................................... 1-2 1.4 FUNCTIONAL PIN DESCRIPTION.................................................................. 1-4 1.4.1 V AND V .............................................................................................. 1 1.4.2 OSC1, OSC2 ............................................................................................... 1-4 1.4.3 RESET......................................................................................................... 1-6 1.4.4 IRQ (MASKABLE INTERRUPT REQUEST)................................................ 1-6 1.4.5 V3.3 ............................................................................................................. 1-6 1.4.6 D+ and D– ................................................................................................... 1-6 1.4.7 PA0-PA7 ...................................................................................................... 1-6 1.4.8 PB0-PB4 ...................................................................................................... 1-7 1.4.9 PC0-PC5...................................................................................................... 1-7 2.1 I/O AND CONTROL REGISTERS ................................................................... 2-2 2.2 RAM ................................................................................................................. 2-2 2.3 ROM................................................................................................................. 2-2 2.4 I/O REGISTERS SUMMARY ........................................................................... 2-3 CENTRAL PROCESSING UNIT 3.1 REGISTERS .................................................................................................... 3-1 3.2 ACCUMULATOR (A)........................................................................................ 3-2 3.3 INDEX REGISTER (X) ..................................................................................... 3-2 3 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Section 4.5 HARDWARE INTERRUPTS ............................................................................ 4-4 4.5.1 External Interrupt IRQ.................................................................................. 4-4 4.5.2 External Interrupt IRQ2................................................................................ 4-5 4.5.3 IRQ Control/Status Register (ICSR) - $0A................................................... 4-6 4.5.4 Port A External Interrupts (PA0-PA3, by mask option) ................................ 4-7 4.5.5 Timer1 Interrupt (TIMER1)........................................................................... 4-8 4.5.6 USB Interrupt (USB) .................................................................................... 4-8 4.5.7 MFT Interrupt (MFT) .................................................................................... 4-8 5.1 POWER-ON RESET ........................................................................................ 5-2 5.2 EXTERNAL RESET ......................................................................................... 5-2 5.3 INTERNAL RESETS ........................................................................................ 5-2 5 ...
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... Freescale Semiconductor, Inc. Section 8.1 OVERVIEW...................................................................................................... 8-2 8.2 COMPUTER OPERATING PROPERLY (COP) WATCHDOG ........................ 8-2 8.3 MFT REGISTERS ............................................................................................ 8-3 8.3.1 Timer Counter Register (TCNT) $09 ........................................................... 8-3 8.3.2 Timer Control/Status Register (TCSR) $08 ................................................. 8-3 8.4 OPERATION DURING STOP MODE .............................................................. 8-4 8.5 COP CONSIDERATION DURING STOP MODE............................................. 8-4 9.1 TIMER REGISTERS (TMRH, TMRL)............................................................... 9-2 9.2 ALTERNATE COUNTER REGISTERS (ACRH, ACRL) .................................. 9-4 9.3 INPUT CAPTURE REGISTERS ...................................................................... 9-5 9 ...
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... Freescale Semiconductor, Inc. Section 10.5.7 USB Status Register (USR)..................................................................... 10-25 10.5.8 USB Endpoint 0 Data Registers (UE0D0-UE0D7)................................... 10-25 10.5.9 USB Endpoint 1/Endpoint 2 Data Registers (UE1D0-UE1D7) ................ 10-26 10.6 USB INTERRUPTS...................................................................................... 10-26 10.6.1 USB End of Transaction Interrupt............................................................ 10-26 10.6.2 Resume Interrupt ..................................................................................... 10-27 10.6.3 End of Packet Interrupt ............................................................................ 10-27 ANALOG TO DIGITAL CONVERTER 11.1 ADC OPERATION ......................................................................................... 11-2 11.2 ADC STATUS AND CONTROL REGISTER (ADSCR).................................. 11-3 11 ...
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... Freescale Semiconductor, Inc. Section MECHANICAL SPECIFICATIONS 14.1 28-PIN PDIP (CASE 710) .............................................................................. 14-1 14.2 28-PIN SOIC (CASE 751F)............................................................................ 14-1 A.1 INTRODUCTION..............................................................................................A-1 A.2 MEMORY .........................................................................................................A-1 A.3 MASK OPTION REGISTER (MOR) .................................................................A-1 A.4 BOOTSTRAP MODE .......................................................................................A-2 A.5 EPROM PROGRAMMING ...............................................................................A-3 A.5.1 EPROM Program Control Register (PCR)...................................................A-3 A.5.2 Programming Sequence ..............................................................................A-3 A.6 EPROM PROGRAMMING SPECIFICATIONS ................................................A-5 MC68HC05JB4 REV 2 For More Information On This Product, ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Section For More Information On This Product, February 24, 1999 TABLE OF CONTENTS Go to: www.freescale.com Page REV ...
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... Freescale Semiconductor, Inc. Section 10.5.7 USB Status Register (USR)..................................................................... 10-25 10.5.8 USB Endpoint 0 Data Registers (UE0D0-UE0D7)................................... 10-25 10.5.9 USB Endpoint 1/Endpoint 2 Data Registers (UE1D0-UE1D7) ................ 10-26 10.6 USB INTERRUPTS...................................................................................... 10-26 10.6.1 USB End of Transaction Interrupt............................................................ 10-26 10.6.2 Resume Interrupt ..................................................................................... 10-27 10.6.3 End of Packet Interrupt ............................................................................ 10-27 ANALOG TO DIGITAL CONVERTER 11.1 ADC OPERATION ......................................................................................... 11-2 11.2 ADC STATUS AND CONTROL REGISTER (ADSCR).................................. 11-3 11 ...
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... Freescale Semiconductor, Inc. Figure 10-11 Regulator Electrical Connections ................................................................. 10-11 10-12 Low Speed Driver Signal Waveforms .......................................................... 10-12 10-13 Differential Input Sensitivity Over Entire Common Mode Range ................. 10-13 10-14 Data Jitter..................................................................................................... 10-14 10-15 Data Signal Rise and Fall Time.................................................................... 10-14 10-16 NRZI Data Encoding .................................................................................... 10-15 10-17 Flow Diagram for NRZI ................................................................................ 10-15 10-18 Bit Stuffing.................................................................................................... 10-16 10-19 Flow Diagram for Bit Stuffing ....................................................................... 10-17 10-20 USB Address Register (UADDR) ...
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... Freescale Semiconductor, Inc. Table 4-1 Reset/Interrupt Vector Addresses .................................................................... 4-1 8-1 RTI and COP Rates at f 10-1 Supported Packet Identifiers .......................................................................... 10-5 10-2 Register Summary ....................................................................................... 10-17 11-1 A/D Channel Assignments ............................................................................. 11-4 12-1 Register/Memory Instructions ........................................................................ 12-4 12-2 Read-Modify-Write Instructions...................................................................... 12-5 12-3 Jump and Branch Instructions........................................................................ 12-6 12-4 Bit Manipulation Instructions .......................................................................... 12-7 12-5 Control Instructions ........................................................................................ 12-7 12-6 Instruction Set Summary............................................................................... 12-8 12-7 Opcode Map................................................................................................. 12-14 13-1 DC Electrical Characteristics.......................................................................... 13-2 13-2 USB DC Electrical Characteristics ................................................................. 13-3 13-3 USB Low Speed Source Electrical Characteristics ...
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... Freescale Semiconductor, Inc. Table For More Information On This Product, LIST OF TABLES Title Go to: www.freescale.com Page ...
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... Freescale Semiconductor, Inc. GENERAL DESCRIPTION The MC68HC05JB4 is a member of the low-cost, high-performance M68HC05 Family of 8-bit microcontroller units (MCUs). The M68HC05 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the popular M68HC05 central processing unit (CPU) and are available with a variety of subsystems, memory sizes and types, and package types. The MC68HC05JB4 is specifi ...
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... Freescale Semiconductor, Inc. • Fully compliant to Low Speed USB with 3 Endpoints: – 1 Control Endpoint (2x8 byte buffer) – 2 Interrupt Endpoints (1x8 byte buffer shared) • 6-channel 8-bit Analog-to-Digital Converter (ADC) • Multi-function Timer (MFT) • 16-bit Timer with 1 input capture and 1 output compare • ...
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... Freescale Semiconductor, Inc. PA0 PA1 PA2 PA3 PA4/IRQ2 PA5 PA6 PA7 PB0/ICAP1 PB1 PB2 PB3/AD4 PB4/AD5 PC0/AD0 PC1/AD1 PC2/AD2 PC3/AD3 PC4/VRH PC5/VRL 8-bit ADC Figure 1-1. MC68HC05JB4 Block Diagram For More Information On This Product, CPU CONTROL ALU 68HC05 CPU ACCUM CPU REGIS- ...
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... Freescale Semiconductor, Inc. PC2/AD2 PC1/AD1 PC0/AD0 PB4/AD5 PB3/AD4 PB0/ICAP1 Figure 1-2. MC68HC05JB4 Pin Assignment 1.4 FUNCTIONAL PIN DESCRIPTION The following paragraphs give a description of the general function of each pin assigned in Fig. 1-2 and Fig. 1-3. 1.4.1 V AND Power is supplied to the MCU through V and V is ground. The MCU operates from a single power supply. ...
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... Freescale Semiconductor, Inc. frequency clock can be derived from a divided by 4 circuit. The type of oscillator is selected by a mask option. An internal 2M OSC1 and OSC2 by a mask option (crystal/ceramic resonator mode only). Crystal Oscillator The circuit in Figure 1-3 (a) shows a typical oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer’ ...
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... Freescale Semiconductor, Inc. 1.4.3 RESET This is an I/O pin. This pin can be used as an input to reset the MCU to a known start-up state by pulling it to the low state. The RESET pin contains a steering diode to discharge any voltage on the pin to V internal pull-up is also connected between this pin and V tains an internal Schmitt trigger to improve its noise immunity as an input ...
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... Freescale Semiconductor, Inc. 1.4.8 PB0-PB4 These five I/O lines comprise Port-B. PB0 to PB4 are push-pull pins with internal pull-up resistors. The state of any pin is software programmable and all Port B lines are configured as inputs during power-on or reset. The internal pull-up resis- tor is software enable. In addition, all Port-B pins have Slow Falling Edge Control which is enabled by software ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. The MC68HC05JB4 has 8k-bytes of addressable memory, with 64 bytes of I/O, 176 bytes of user RAM, and 3584 bytes of user ROM, as shown in Figure 2-1 . $0000 I/O Registers 64 Bytes $003F $0040 Unused 64 Bytes $007F $0080 User RAM 176 Bytes $00C0 64 Byte Stack $00FF $012F $0130 ...
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... Freescale Semiconductor, Inc. 2.1 I/O AND CONTROL REGISTERS The I/O and Control Registers reside in locations $0000 to $003F. The bit assign- ments for each register are shown in Figure 2-2, Figure 2-3, Figure 2-4, and Figure 2-5. Reading from unused bits will return unknown states, and writing to unused bits will be ignored. ...
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... Freescale Semiconductor, Inc. 2.4 I/O REGISTERS SUMMARY ADDR REGISTER R/W Port A Data R $0000 PORTA W Port B Data R $0001 PORTB W Port C Data R $0002 PORTC W R $0003 Unused W Port A Data Direction R $0004 DDRA W Port B Data Direction R $0005 SLOWEASLOWEB DDRB W Port C Data Direction R $0006 DDRC W R $0007 Unused ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION ADDR REGISTER R/W Port A Pull-Up R $0010 PURA W Port B Pull-Up R $0011 PURB W Timer1 Control R $0012 TCR W Timer1 Status R $0013 TSR W Input Capture MSB R $0014 ICH W Input Capture LSB R $0015 ICL W Output Compare MSB R $0016 OCH W Output Compare LSB ...
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... Freescale Semiconductor, Inc. ADDR REGISTER R/W R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 USB Endpoint 0 Data 0 $0020 UD0R0 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 USB Endpoint 0 Data 1 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 $0021 UD0R1 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION ADDR REGISTER R/W R $0030 Unused W R $0031 Unused W R $0032 Unused W R $0033 Unused W R $0034 Unused W R $0035 Unused W R $0036 Unused W USB Control 2 R $0037 UCR2 W USB Address R $0038 UADR W USB Interrupt 0 R $0039 ...
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... Freescale Semiconductor, Inc. CENTRAL PROCESSING UNIT The MC68HC05JB4 has an 8k-bytes memory map. The stack has only 64 bytes. Therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00C0 and then wrap-around to $00FF. All other instructions and registers behave as described in this chapter. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 3.2 ACCUMULATOR (A) The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The CPU uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. The accumulator is not affected by a reset of the device. 3.3 INDEX REGISTER (X) The index register shown in Figure 3 8-bit register that can perform two functions: • ...
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... Freescale Semiconductor, Inc. Normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.6 CONDITION CODE REGISTER (CCR) The CCR shown in Figure 3 5-bit register in which four bits are used to indicate the results of the instruction just executed. The fi ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 3.6.5 Carry/Borrow Bit (C-Bit) The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates ...
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... Freescale Semiconductor, Inc. The MCU can be interrupted in seven different ways: • Non-maskable Software Interrupt Instruction (SWI) • External Asynchronous Interrupt (IRQ) • External Asynchronous Interrupt (IRQ2) • Optional External Interrupt via IRQ on PA0-PA3 (by a mask option) • USB Interrupt • Timer1 Interrupt (16-bit Timer) • ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION If more than one interrupt request is pending, the CPU fetches the vector of the higher priority interrupt first. A higher priority interrupt does not actually interrupt a lower priority interrupt service routine unless the lower priority interrupt service routine clears the I bit. ...
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... Freescale Semiconductor, Inc. FROM RESET YES I BIT SET? NO EXTERNAL INTERRUPT? NO USB INTERRUPT? NO TIMER1 INTERRUPT? NO MFT INTERRUPT? NO FETCH NEXT INSTRUCTION. SWI INSTRUCTION? NO RTI INSTRUCTION? NO Figure 4-2. Interrupt Flowchart MC68HC05JB4 REV 2 For More Information On This Product, February 24, 1999 GENERAL RELEASE SPECIFICATION I YES CLEAR IRQ LATCH. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 4.3 RESET INTERRUPT SEQUENCE The RESET function is not in the strictest sense an interrupt; however acted upon in a similar manner as shown in Figure 4-2. A low level input on the RESET pin or an internally generated RST signal causes the program to vector to its start- ing address which is specifi ...
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... Freescale Semiconductor, Inc. The IRQE enable bit controls whether an active IRQF flag can generate an IRQ interrupt sequence. This interrupt is serviced by the interrupt service routine located at the address specified by the contents of $1FFA and $1FFB. If IRQF is set, the only way to clear this fl writing a logic one to the IRQR acknowledge bit in the ICSR. As long as the output state of the IRQF fl ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION IRQ2 Figure 4-4. External Interrupt (IRQ2) Logic 4.5.3 IRQ Control/Status Register (ICSR) - $0A The IRQ interrupt function is controlled by the ICSR located at $000A. All unused bits in the ICSR will read as logic zeros. The IRQF bit is cleared and IRQE bit is set by reset ...
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... Freescale Semiconductor, Inc. IRQE — IRQ Interrupt Enable The IRQE bit enables/disables the IRQF flag bit to initiate an IRQ interrupt sequence Enables IRQ interrupt, that is, the IRQF flag bit can generate an interrupt sequence. Reset sets the IRQE enable bit, thereby enabling IRQ interrupts once the I-bit is cleared. Execution of the STOP or WAIT instructions causes the IRQE bit to be set in order to allow the external IRQ to exit these modes ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION The BIH and BIL instructions will only apply to the level on the IRQ pin itself, and not to the output of the logic OR function with the PA0 to PA3 pins. The state of the individual Port A pins can be checked by reading the appropriate Port A pins as inputs ...
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... Freescale Semiconductor, Inc. This section describes the six reset sources and how they initialize the MCU. A reset immediately stops the operation of the instruction being executed, initializes certain control bits, and loads the program counter with a user defined reset vec- tor address. The following conditions produce a reset: • ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 5.1 POWER-ON RESET A positive transition on the V reset is strictly for conditions during powering up and cannot be used to detect drops in power supply voltage. A 4064 t (internal clock cycle) delay after the oscillator becomes active allows CYC the clock generator to stabilize. If the RESET pin is at logic zero at the end of the ...
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... Freescale Semiconductor, Inc. The POR will generate the RST signal which will reset the CPU. If any other reset function is active at the end of the 4064 cycle delay, the RST signal will remain in the reset condition until the other reset condition(s) end. POR will not activate the pulldown device on the RESET pin. V ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 5.3.5 Illegal Address Reset An opcode fetch from an address that is not in the ROM (locations $1000 to $1FFF) or the RAM (locations $0080 to $012F) generates an illegal address reset. The illegal address reset will assert the pulldown device to pull the RESET pin low for cycles of the internal bus clock ...
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... Freescale Semiconductor, Inc. There are three modes of operation that reduce power consumption: • Stop mode • Wait mode • Data retention mode Figure 6-1 shows the sequence of events in Stop and Wait modes. MC68HC05JB4 REV 2 For More Information On This Product, February 24, 1999 GENERAL RELEASE SPECIFICATION ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION STOP STOP EXTERNAL OSCILLATOR, STOP INTERNAL TIMER CLOCK, RESET START-UP DELAY STOP INTERNAL PROCESSOR CLOCK, CLEAR I-BIT IN CCR, SET IRQE IN ICSR YES EXTERNAL RESET? NO IRQ YES EXTERNAL INTERRUPT? NO IRQ2 YES EXTERNAL INTERRUPT? NO USB YES INTERRUPT ...
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... Freescale Semiconductor, Inc. 6.1 STOP MODE STOP mode is entered by executing the STOP instruction. This is the lowest power consumption mode of the MCU. In the STOP Mode the internal oscillator is turned off, halting all internal processing. Execution of the STOP instruction automatically clears the I-bit in the Condition Code Register and sets the IRQE enable bit in the IRQ Control/Status Register so that the IRQ external interrupt is enabled ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION For More Information On This Product, February 24, 1999 LOW POWER MODES Go to: www.freescale.com REV ...
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... Freescale Semiconductor, Inc. In normal operating mode there are 19 usable bidirectional I/O lines arranged as one 8-bit I/O port (Port-A), one 5-bit I/O port (Port-B), and one 6-bit I/O port (Port C). The individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (DDRs). ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 7.2 PORT-A Port 8-bit bi-directional port. The port-A data register is at $0000 and the data direction register (DDRA $0004. Reset does not affect the data regis- ters, but clears the data direction registers, thereby returning the port pins to inputs. Writing a ‘ ...
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... Freescale Semiconductor, Inc. 7.2.2 Port-A Data Direction Register BIT 7 BIT 6 DDRA R DDRA7 DDRA6 $0004 W reset: 0 7.2.3 Port-A Pull-up Control Register BIT 7 BIT 6 PURA R $0010 W PURA7 PURA6 reset: 0 7.3 PORT-B Port 5-bit bi-directional port. The port-B data register is at $0001 and the data direction register (DDRB $0005. Reset does not affect the data regis- ters, but clears the data direction registers, thereby returning the port pins to inputs. Writing a ‘ ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Enabling or disabling the SLOW edge function does not change the pin configuration. Reading from an output pin will return the content of the data register. 7.3.1 Port-B Data Register BIT 7 BIT 6 PTB R 0 $0001 W reset: 0 7.3.2 Port-B Data Direction Register ...
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... Freescale Semiconductor, Inc. selected. When a port pin is selected as ADC input and the ADON bit is set to ‘1’, the pin will be configured as input pin automatically regardless of the status of the DDR-bit. The value of the DDR-bit will not be affected. Port-C DDRX Reading from an output pin will return the content of the data register. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION For More Information On This Product, February 24, 1999 INPUT/OUTPUT PORTS Go to: www.freescale.com REV ...
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... Freescale Semiconductor, Inc. MULTI-FUNCTION TIMER The Multi-Function Timer module is a 15-stage ripple counter with Timer Over Flow (TOF), Real Time Interrupt (RTI), and COP Watchdog function Timer Counter Register ($09) 10 ÷2 17 ÷2 ÷2 RTI Select Circuit Overflow Detect Circuit Timer Control & Status Register ($08) ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8.1 OVERVIEW As shown in Figure 8-1, the Timer is driven by the timer clock, NTF1, divided by four. NTF1 has the same phase and frequency as the processor bus clock, PH2, but continues to run in WAIT mode. The NTF1 drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by accessing the Timer Counter Register (TCNT) at address $09. A timer overfl ...
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... Freescale Semiconductor, Inc. 8.3 MFT REGISTERS 8.3.1 Timer Counter Register (TCNT) $09 The Timer Counter Register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at f ÷4 and can be used for various functions including a software input OP capture ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION RTIF - Real Time Interrupt Flag The RTIF is a read-only flag bit Set when the output of the chosen ( selections) Real Time Interrupt stage goes active. A TIMER Interrupt request will be generated if RTIE is also set Reset by writing a logical one to the RTIF acknowledge bit, RTIFR. ...
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... Freescale Semiconductor, Inc. This 16-bit Programmable Timer (Timer1) has an Input Capture function and an Output Compare function. Figure 9-1 shows a block diagram of the 16-bit pro- grammable timer. EDGE SELECT ICAP1 & DETECT LOGIC RESET TIMER CONTROL REGISTER $0012 INTERNAL DATA BUS Figure 9-1. Programmable Timer Block Diagram ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION The basis of the 16-bit Timer is a 16-bit free-running counter which increases in count with each internal bus clock cycle. The counter is the timing reference for the input capture and output compare functions. The input capture and output ...
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... Freescale Semiconductor, Inc. The timer registers (TMRH, TMRL) shown in Figure 9-3 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the timer registers has no effect. Reset of the device presets the timer counter to $FFFC. BIT 7 BIT 6 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 9.2 ALTERNATE COUNTER REGISTERS (ACRH, ACRL) The functional block diagram of the 16-bit free-running timer counter and alternate counter registers is shown in Figure 9-4. The alternate counter registers behave the same as the timer registers, except that any reads of the alternate counter will not have any effect on the TOF fl ...
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... Freescale Semiconductor, Inc. To prevent interrupts from occurring between readings of the ACRH and ACRL, set the I bit in the condition code register (CCR) before reading ACRH and clear the I bit after reading ACRL. 9.3 INPUT CAPTURE REGISTERS The input capture function is a technique whereby an external signal (connected to PB0/ICAP1 pin) is used to trigger the 16-bit timer counter ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION The result obtained by an input capture will be one count higher than the value of the free-running timer counter preceding the external transition. This delay is required for internal synchronization. Resolution is affected by the prescaler, allowing the free-running timer counter to increment once every four internal clock cycles (eight oscillator clock cycles) ...
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... Freescale Semiconductor, Inc. Writing to the OCRH before writing to the OCRL inhibits timer compares until the OCRL is written. Reading or writing to the OCRL after reading the TSR will clear the output compare flag bit (OCF). R/W OCRH ($0016) OCRH 16-BIT COMPARATOR ($FFFC) RESET TIMER CONTROL REG. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION A software example of this procedure is shown below. 9B SEI ... ... ... ... B7 16 STA B6 13 LDA BF 17 STX ... ... ... ... 9A CLI 9.5 TIMER CONTROL REGISTER (TCR) The timer control register is shown in Figure 9-10 performs the following func- tions: • Enables input capture interrupts • ...
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... Freescale Semiconductor, Inc. IEDG - INPUT CAPTURE EDGE SELECT The state of this read/write bit determines whether a positive or negative transi- tion on the ICAP1 pin triggers a transfer of the contents of the timer register to the input capture register. Reset has no effect on the IEDG bit Positive edge (low to high transition) triggers input capture. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 9.7 TIMER OPERATION DURING WAIT MODE During WAIT mode the 16-bit timer continues to operate normally and may gener- ate an interrupt to trigger the MCU out of the WAIT mode. 9.8 TIMER OPERATION DURING STOP MODE When the MCU enters the STOP mode the free-running counter stops counting (the internal processor clock is stopped) ...
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... Freescale Semiconductor, Inc. UNIVERSAL SERIAL BUS MODULE This USB Module is designed for USB application in LS products. With minimized software effort, it can fully comply with USB LS device specification. See USB specification version 1.0 for the detail description of USB. 10.1 FEATURES • Integrated 3.3 Volt Regulator with 3.3V Output Pin • ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 10.2 OVERVIEW This section provides an overview of the Universal Serial Bus (USB) module in the MC68HC05JB4. This USB module is designed to serve as a low-speed (LS) USB device per the Universal Serial Bus Specification Rev 1.0. Three types of USB data transfers are supported: control, interrupt, and bulk (transmit only). Endpoint 0 functions as a receive/transmit control endpoint ...
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... Freescale Semiconductor, Inc. ENDPOINT 0 TRANSACTIONS: Control Write SETUP DATA0 ACK OUT DATA0 Control Read SETUP DATA0 ACK IN DATA0 No-Data Control SETUP DATA0 ACK ENDPOINTS 1 & 2 TRANSACTIONS: Interrupt IN DATA0/1 Bulk Transmit IN DATA0/1 Figure 10-2. Supported Transaction Types per Endpoint Each USB transaction is comprised of a series of packets. The MC68HC05JB4 USB module supports the packet types shown in Figure 10-3 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Token Packet: IN OUT SETUP Data Packet: DATA0 DATA1 Handshake Packet: ACK NAK STALL Figure 10-3. Supported USB Packet Types The following sections will give some detail on each segment used to form a complete USB transaction. 10.2.1.1 Sync Pattern The NRZI (See Section 10.4.4.1) bit pattern shown in Figure 10-4 is used as a synchronization pattern and is prefi ...
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... Freescale Semiconductor, Inc. V (min (max (min (min SOP BUS IDLE Figure 10-5. SOP, Sync Signaling and Voltage Levels 10.2.1.2 Packet Identifier Field The Packet Identifier field is an eight bit number comprised of the four bit packet identification (PID) and its complement. The field follows the sync pattern and determines the direction and type of transaction on the bus ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 10.2.1.4 Endpoint Field (ENDP) The Endpoint field is a four bit number that is used to select a particular endpoint within a USB device. For the MC68HC05JB4, this will be a binary number between zero and two inclusive. Any other value will cause the transaction to be ignored ...
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... Freescale Semiconductor, Inc. - Update every bit time - Reset to ones at SOP Input / Output Data Stream next bit Output TRANSMIT Data Stream CRC16 Transmitted MSB first after final data byte. Figure 10-7. CRC Block Diagram for Data Packets 10.2.1.6 End Of Packet (EOP) The single-ended 0 (SE0) state is used to signal an end of packet (EOP). The single-ended 0 state is indicated by both D+ and D– ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION V (min (max (min (min Figure 10-8. EOP Transaction Voltage Levels The width of the SE0 in the EOP is about two bit times. The EOP width is measured with the same capacitive load used for maximum rise and fall times and is measured at the same level as the differential signal crossover points of the data lines ...
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... Freescale Semiconductor, Inc. Reset can wake a device from the suspended mode. A device may take up to 10ms to wake up from the suspended state. 10.2.3 Suspend The MC68HC05JB4 supports suspend mode for low power. Suspend mode should be entered when the USB data lines are in the idle state for more than 3.0 ms ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION When using the remote wake-up capability, the firmware must wait for at least 5 ms after the bus is in the idle state before sending the remote wake-up resume signaling. This allows the upstream devices to get into their suspend state and prepare for propagating resume signaling ...
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... Freescale Semiconductor, Inc. USB registers. The following will detail the function of the regulator, transceiver and control logic. See Section 10.5 for the register discussion. 10.4.1 Voltage Regulator The USB data lines are required by the USB Specification to have a maximum output voltage between 2.8V and 3.6V. The data lines are also required to have an external 1 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION with respect to local ground reference without damage. 10.4.2.2 Low Speed (1.5 Mbs) Driver Characteristics The rise and fall time of the signals on this cable are greater than keep RFI emissions under FCC class B limits, and less than 300 ns to limit timing delays and signaling skews and distortions. The driver reaches the specifi ...
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... Freescale Semiconductor, Inc. 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 Figure 10-13. Differential Input Sensitivity Over Entire Common Mode Range 10.4.3.1 Receiver Data Jitter The data receivers for all types of devices must be able to properly decode the differential data in the presence of jitter. The more of the bit cell that any data edge can occupy and still be decoded, the more reliable the data transfer will be ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION t Period DIFFERENTIAL DATA LINES For low speed transmissions, the jitter time for any consecutive differential data transitions must be within differential data transitions. These jitter numbers include timing variations due to differential buffer delay, rise/fall time mismatches, internal clock source jitter, and to noise and other random effects ...
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... Freescale Semiconductor, Inc. When transmitting, the control logic handles parallel to serial conversion, CRC generation, NRZI encoding, and bit stuffing. When Receiving, the control logic handles Sync detection, packet identification, end of packet detection, bit (un)stuffing, NRZI decoding, CRC validation, and serial to parallel conversion. Errors detected by the control logic include bad CRC, time-out while waiting for EOP, and bit stuffi ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 10.4.4.2 Bit Stuffing In order to ensure adequate signal transitions, bit stuffing is employed by the transmitting device when sending a packet on the USB (see Figure 10-18 and Figure 10-19 inserted after every six consecutive 1’s in the data stream before the data is NRZI encoded to force a transition in the NRZI data stream. ...
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... Freescale Semiconductor, Inc. NO PACKET TRANSMISSION Figure 10-19. Flow Diagram for Bit Stuffing 10.5 I/O REGISTER DESCRIPTION The USB Endpoint registers are comprised of a set of control/status registers and twenty-four data registers that provide storage for the buffering of data between the USB and the CPU. These registers are shown in Table 10-2. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Register Name Bit 7 USB Control Register 2 (UCR2) USB Address Register USBEN (UADDR) TXD0F USB Interrupt Register 0 (UIR0) TXD1F USB Interrupt Register 1 (UIR1) USB Control Register 0 T0SEQ (UCR0) USB Control Register 1 T1SEQ ENDADD (UCR1) RSEQ USB Status Register ...
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... Freescale Semiconductor, Inc. USBEN — USB Module Enable This read/write bit enables and disables the USB module and the USB pins. When USBEN is clear, the USB module will not respond to any tokens. Reset clears this bit USB function enabled 0 = USB function disabled UADD6-UADD0 — ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION SUSPND — USB Suspend Flag To save power, this read/write bit should be set by the software if a 3ms con- stant idle state is detected on USB bus. Setting this bit stops the clock to the USB and causes the USB module to enter Suspend mode. Unnecessary ana- log circuitry will be powered down. Software must clear this bit after the Resume fl ...
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... Freescale Semiconductor, Inc. EOPF — End of Packet Detect Flag This read only bit is set when a valid End-of-Packet sequence is detected on the D+ and D– lines. Software must clear this flag by writing a logic 1 to the EOPFR bit. Reset clears this bit. Writing a logic 0 to EOPF has no effect. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION T0SEQ — Endpoint 0 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction. Toggling of this bit must be controlled by software. Reset clears this bit DATA1 Token active for next Endpoint 0 transmit 0 = DATA0 Token active for next Endpoint 0 transmit STALL0 — ...
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... Freescale Semiconductor, Inc. T1SEQ — Endpoint1/Endpoint 2 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed to Endpoint 1 or Endpoint 2. Toggling of this bit must be controlled by software. Reset clears this bit DATA1 Token active for next Endpoint 1/Endpoint 2 transmit 0 = DATA0 Token active for next Endpoint 1/Endpoint 2 transmit ENDADD — ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION TX1STR — Clear Transmit First Flag Writing a logic 1 to this write-only bit will clear the TX1ST bit set. Writing a logic 0 to the TX1STR has no effect. Reset clears this bit. TX1ST — Transmit First Flag ...
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... Freescale Semiconductor, Inc. 10.5.7 USB Status Register (USR) BIT 7 BIT 6 USR R RSEQ SETUP $003D W reset Unimplemented Figure 10-26. USB Status Register (USR) RSEQ — Endpoint 0 Receive Sequence Bit This read only bit indicates the type of data packet last received for Endpoint 0 (DATA0 or DATA1). ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 10.5.9 USB Endpoint 1/Endpoint 2 Data Registers (UE1D0-UE1D7) BIT 7 BIT 6 UE1D0 R UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 $0028 UE1D7 R UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 $002F W reset: X Figure 10-28. USB Endpoint 1/Endpoint2 Data Registers (UE1D0-UE1D7) UE1TD7 - UE1TD0 — ...
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... Freescale Semiconductor, Inc. a SETUP interrupt are shown in Figure 10-30. 10.6.1.2 Transmit Control Endpoint 0 For a Control IN transaction directed at Endpoint 0, the USB module will generate an interrupt by setting the TXD0F flag in the UIR0 register. The conditions necessary for the interrupt to occur are shown in the flowchart of Figure 10-31. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Valid OUT token received for Endpoint 0 Y Valid DATA token received for Endpoint 0? Y Endpoint 0 Receive Enabled? (USBEN = 1) Y Endpoint 0 Receive Not Stalled? (STALL0 = 0) Y Endpoint 0 Receive Ready to Receive? (RX0E = 1) && (RXD0F = 0) Y Accept Data ...
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... Freescale Semiconductor, Inc. Valid SETUP token received for Endpoint 0 Y Endpoint 0 Receive Enabled? (USBEN = 1) Y Endpoint 0 Receive Ready to Receive? (RX0E = 1) && (RXD0F = 0) Y STALL0 = 0? Y Accept Data set/clear RSEQ bit Set SETUP Error free DATA packet? Y Set RXD0F ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Valid IN token received for Endpoint 0 Y Transmit Endpoint Enabled? (USBEN = 1) Y Transmit Endpoint not Stalled by firmware? (STALL0 = 0) Y Transmit Endpoint ready to Transfer? (TX0E = 1) && (TXD0F = 0) Y Send DATA Data PID set by T0SEQ ACK received and no ...
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... Freescale Semiconductor, Inc. Valid IN token received for Endpoints Transmit Endpoint Enabled? (USBEN = 1) Y Transmit Endpoint not Stalled by firmware? (STALL1 & ENDP1) + (STALL2 & ENDP2) Y Transmit Endpoint ready to Transfer? (TX1E = 1) && (TXD1F = 0) & ((ENDP2 & ENDADD) + (ENDP1 & ENDADD)) ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION UNIVERSAL SERIAL BUS MODULE For More Information On This Product, February 24, 1999 Go to: www.freescale.com REV ...
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... Freescale Semiconductor, Inc. ANALOG TO DIGITAL CONVERTER The analog to digital converter system consists of a single 8-bit successive approximation converter and an 16-channel analog multiplexer. Six of the chan- nels are available for analog inputs, four channels are dedicated to internal test functions, and the remaining six channels are unused. There is one 8-bit ADC Data Register ($0F) and one 8-bit ADC Status and Control register ($0E) ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 11.1 ADC OPERATION As shown in Figure 11-1, the ADC consists of an analog multiplexer, an 8-bit digi- tal to analog capacitor array, a comparator and a successive approximation regis- ter (SAR). There are ten options that can be selected by the multiplexer; the AD0 to AD5 ...
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... Freescale Semiconductor, Inc. 11.2 ADC STATUS AND CONTROL REGISTER (ADSCR) The ADSCR is a read/write register containing status and control bits for the ADC. BIT 7 BIT 6 ADSCR R COCO ADRC $000E W reset: 0 Figure 11-2. A/D Status and Control Register COCO — COnversion COmplete ADC conversion has completed; ADC Data Register ($0F) contains valid conversion result ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 11-1. A/D Channel Assignments CH3 CH2 CH1 Using a port pin as both an analog and digital input simultaneously is prohib- ited ...
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... Freescale Semiconductor, Inc. 11.4 ADC DURING LOW POWER MODES The ADC continues normal operation in WAIT mode. To reduce power consump- tion in WAIT mode, the ADON and ADRC bits in the ADSCR should be cleared if the ADC is not used. If the ADC is in use and the internal bus clock is above 1MHz recommended that the ADRC bit be cleared ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION ANALOG TO DIGITAL CONVERTER For More Information On This Product, February 24, 1999 Go to: www.freescale.com REV ...
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... Freescale Semiconductor, Inc. This section describes the addressing modes and instruction types. 12.1 ADDRESSING MODES The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes define the manner in which the CPU finds the data required to execute an instruction. The eight addressing modes are the following: • ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.1.3 Direct Direct instructions can access any of the first 256 memory addresses with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address ...
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... Freescale Semiconductor, Inc. 12.1.7 Indexed, 16-Bit Offset Indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the conditional address of the operand. The fi ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.1.10 Register/Memory Instructions Most of these instructions use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 12-1 lists the register/memory instructions. Table 12-1. Register/Memory Instructions Add Memory Byte and Carry Bit to Accumulator ...
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... Freescale Semiconductor, Inc. 12.1.11 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. The test for negative or zero instruction (TST exception to the read-modify-write sequence because it does not write a replacement value. Table 12-2 lists the read-modify-write instructions ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. ...
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... Freescale Semiconductor, Inc. 12.1.13 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory. Port registers, port data direction registers, timer registers, and on-chip RAM locations are in the first 256 bytes of memory. The CPU can also test and branch based on the state of any bit in any of the fi ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.1.15 Instruction Set Summary Table 12 alphabetical list of all M68HC05 instructions and shows the effect of each instruction on the condition code register. Table 12-6. Instruction Set Summary Source Operation Form ADC # opr ADC opr ADC opr Add with Carry ...
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... Freescale Semiconductor, Inc. Table 12-6. Instruction Set Summary (Continued) Source Operation Form Branch if Half-Carry BHCS rel Bit Set BHI rel Branch if Higher Branch if Higher or BHS rel Same Branch if IRQ Pin BIH rel High Branch if IRQ Pin BIL rel Low BIT # opr BIT opr ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 12-6. Instruction Set Summary (Continued) Source Operation Form BSET n opr Set Bit n Branch to BSR rel Subroutine CLC Clear Carry Bit CLI Clear Interrupt Mask CLR opr CLRA CLRX Clear Byte CLR opr ,X CLR ,X CMP # opr ...
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... Freescale Semiconductor, Inc. Table 12-6. Instruction Set Summary (Continued) Source Operation Form INC opr INCA INCX Increment Byte INC opr ,X INC ,X JMP opr JMP opr JMP opr ,X Unconditional Jump JMP opr ,X JMP ,X JSR opr JSR opr JSR opr ,X Jump to Subroutine JSR opr ,X ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 12-6. Instruction Set Summary (Continued) Source Operation Form ORA # opr ORA opr Logical OR ORA opr Accumulator with ORA opr ,X Memory ORA opr ,X ORA ,X ROL opr ROLA Rotate Byte Left ROLX through Carry Bit ROL opr ,X ...
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... Freescale Semiconductor, Inc. Table 12-6. Instruction Set Summary (Continued) Source Operation Form SUB # opr SUB opr Subtract Memory SUB opr Byte from SUB opr ,X Accumulator SUB opr ,X SUB ,X SWI Software Interrupt Transfer TAX Accumulator to Index Register TST opr TSTA Test Memory Byte ...
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Bit Manipulation Branch DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR BRCLR0 BCLR0 BRN ...
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... Freescale Semiconductor, Inc. ELECTRICAL SPECIFICATIONS This section describes the electrical and timing specifications of the MC68HC05JB4. 13.1 MAXIMUM RATINGS (Voltages referenced Rating Supply Voltage Current Drain Per Pin Excluding V and V DD Input Voltage IRQ/V Pin PP Storage Temperature Range Maximum ratings are the extreme limits the device can be exposed to without causing permanent damage to the chip ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 13.3 DC ELECTRICAL CHARACTERISTICS Table 13-1. DC Electrical Characteristics (V = 4.2V to 5.5V Vdc Characteristic Output Voltage I = 10.0 A Load Output High Voltage (I =–0.8 mA) PA0-7, PB0-4, PC0-5 Load Output Low Voltage (I Load = 1.6 mA) PA0-4, PB0-4, PC0-5 (I Load = 10.0 mA) PA5-7 (I Load = 25.0 mA) PA6, PA7 (mask option) ...
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... Freescale Semiconductor, Inc. NOTES: 1. All values shown reflect average measurements. 2. Typical values at midpoint of voltage range only. 3. Wait I : Only MFT and Timer1 active Run (Operating Wait I DD MHz), all inputs 0.2 VDC from rail loads, less than 50pF on all outputs ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 13.5 USB LOW SPEED SOURCE ELECTRICAL CHARACTERISTICS Table 13-3. USB Low Speed Source Electrical Characteristics Parameter Transition time: Rise Time Fall Time Rise/Fall Time Matching Output Signal Crossover Voltage Low Speed Data Rate Source Differential Driver Jitter ...
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... Freescale Semiconductor, Inc. 13.6 CONTROL TIMING (V = 4.2V to 5.5V Vdc Characteristic Frequency of Operation Crystal Oscillator Option External Clock Source Internal Operating Frequency Crystal Oscillator (f 2) OSC External Clock (f 2) OSC Cycle Time (1 RESET Pulse Width Low IRQ Interrupt Pulse Width Low (Edge-Triggered) ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION For More Information On This Product, February 24, 1999 ELECTRICAL SPECIFICATIONS Go to: www.freescale.com REV ...
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... Freescale Semiconductor, Inc. MECHANICAL SPECIFICATIONS This section provides the mechanical dimensions for the 28-pin PDIP and 28-pin SOIC packages. 14.1 28-PIN PDIP (CASE 710 SEATING PLANE 14.2 28-PIN SOIC (CASE 751F) - 28X 0.010 (0.25 26X ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION For More Information On This Product, February 24, 1999 MECHANICAL SPECIFICATIONS Go to: www.freescale.com REV ...
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... Freescale Semiconductor, Inc. This appendix describes the MC68HC705JB4, the emulation part for MC68HC05JB4. The entire MC68HC05JB4 data sheet applies to the MC68HC705JB4, with exceptions outlined in this appendix. A.1 INTRODUCTION The MC68HC705JB4 is an EPROM version of the MC68HC05JB4, and is avail- able for user system evaluation and debugging. The MC68HC705JB4 is function- ally identical to the MC68HC05JB4 with the exception of the 3584 bytes user ROM is replaced by 3584 bytes user EPROM ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION PAINTEN – PA0-PA3 External Interrupt Options 1 = External interrupt capability on PA0-PA3 disabled External interrupt capability on PA0-PA3 enabled. OSCDLY – Oscillator Delay Option 1 = 128 internal clock cycles 4064 internal clock cycles. LVREN – LVR Option 1 = Low Voltage Reset circuit enabled. ...
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... Freescale Semiconductor, Inc. The user code must be a one-to-one correspondence with the internal EPROM addresses. A.5 EPROM PROGRAMMING Programming the on-chip EPROM is achieved by using the Program Control Reg- ister located at address $3E. Please contact Freescale for programming board availability. A.5.1 EPROM Program Control Register (PCR) This register is provided for programming the on-chip EPROM in the MC68HC705JB4 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION It is important to remember that an external programming voltage must be applied to the V pin while programming, but it should be equal operations. Figure A-2 shows the flow required to successfully program the EPROM. Figure A-2. EPROM Programming Sequence For More Information On This Product, ...
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... Freescale Semiconductor, Inc. A.6 EPROM PROGRAMMING SPECIFICATIONS Table A-1. EPROM Programming Electrical Characteristics ( Vdc, T 4. Characteristic Programming Voltage IRQ/V PP Programming Current IRQ/V PP Programming Time per byte A.7 DC ELECTRICAL CHARACTERISTICS Table A-2. DC Electrical Characteristics (705JB4 4.2V to 5.5V Vdc +40 C, unless otherwise noted) ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION For More Information On This Product, February 24, 1999 Go to: www.freescale.com REV ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center ...