mc68hc05jb4p Freescale Semiconductor, Inc, mc68hc05jb4p Datasheet - Page 49

• Manufacturer Part Number: mc68hc05jb4p
• Description: Mc68hc705jb4 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

7.2.2 Port-A Data Direction Register
7.2.3 Port-A Pull-up Control Register
7.3
MC68HC05JB4
REV 2
PORT-B
Port-B is a 5-bit bi-directional port. The port-B data register is at $0001 and the
data direction register (DDRB) is at $0005. Reset does not affect the data regis-
ters, but clears the data direction registers, thereby returning the port pins to
inputs. Writing a ‘one’ to a DDR bit sets the corresponding port bit to output mode.
Each pin in Port-B has an internal pull-up resistor (50k
individually enabled by writing a ‘1’ to the corresponding bit in the Port-B pull-up
control register at location $0011.
All Port-B pins have built in Slow Output edge transition driver which can be
enabled by writing a ‘1’ to bit-6 of Port-B data direction register at location $0005.
When PB0 is configured as an input, it also serves as the input capture pin for the
16-bit Timer. When configured as output, the input to the input capture will be per-
manently tied “low” and no input capture can be generated. PB0 has built-in
schmitt triggered input to improve noise immunity.
PB3 and PB4 also serve as extra ADC inputs, AD4 and AD5. When a port pin is
selected as ADC input and the ADON bit is set to ‘1’, the pin will be configured as
input pin and its pull-up will be disabled automatically regardless of the status of
the DDR-bit. The value of the DDR-bit will not be affected.
If the pull-up device is enabled and the port pin is configured as output, the output
port becomes an open-drain output with 50k pull-up.
DDRA
$0004
PURA
$0010
reset:
reset:
W
W
R
R
Port-B PURX
DDRA7
PURA7
BIT 7
BIT 7
0
0
0
0
1
1
Freescale Semiconductor, Inc.
For More Information On This Product,
DDRA6
PURA6
BIT 6
BIT 6
0
0
Port-B DDRX
Go to: www.freescale.com
INPUT/OUTPUT PORTS
0
1
0
1
February 24, 1999
DDRA5
PURA5
BIT 5
BIT 5
0
0
Open-drain Output with 50k pull-up
DDRA4
PURA4
BIT 4
BIT 4
0
0
Input with 50k pull-up
Pin Configuration
Output Push/Pull
DDRA3
PURA3
GENERAL RELEASE SPECIFICATION
BIT 3
BIT 3
Input
0
0
DDRA2
PURA2
BIT 2
BIT 2
0
0
typical) which can be
DDRA1
PURA1
BIT 1
BIT 1
0
0
DDRA0
PURA0
BIT 0
BIT 0
0
0