mc68hc05l25 Freescale Semiconductor, Inc, mc68hc05l25 Datasheet - Page 80

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mc68hc05l25

Manufacturer Part Number
mc68hc05l25
Description
M68hc05 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Oscillators and Clock
8.10 XOSC
The oscillator (XOSC) runs continuously after power-up. The XOSC never stops while power is applied.
XOSC pins have options for feedback and damping resistor implementations. These options are set
through mask option and may be read through the mask option status register (MOSR). See
Options.
8.11 Stop and Wait Modes
Power reduction can be achieved by executing the STOP instruction and halting the CPU. During stop
mode, the CPU and all modules except time base are halted. The stop mode is exited by external RESET,
COP reset, IRQ, SPI (slave mode), or TB interrupt. The CPU resumes immediately from stop mode since
XOSC never stops oscillating during stop mode.
The CPU clock is halted and the peripheral modules are not affected during wait mode. Wait mode is
exited by RESET or any interrupts.
8.12 Miscellaneous Register
FTUP — OSC Time Up Flag
80
Power-on detection and clearing FOSCE bit clears this bit. This bit is set by the overflow of the POR
counter. A reset does not affect this bit.
Read:
1 = OSC clock available for the system clock
0 = During POR or OSC shut down
NOTE: Power-on reset is strictly for power-on conditions and does not detect a drop in power.
Address:
Reset or Interrupt
Reset:
Read:
Write:
Mode Before
Power Off
Stop/Wait
Run
$003E
FTUP
Bit 7
U
Figure 8-4. Miscellaneous Register (MISC)
Table 8-3. Recovery Time Requirements
= Unimplemented
STUP
U
6
Power-On Reset
MC68HC05L25 Data Sheet, Rev. 3.1
See Note
See Note
Delay
5
0
0
Delay Time After Reset or Interrupt
4
0
0
External RESET
U = Unaffected
SYS1
COP and
No Delay
No Delay
3
0
SYS0
2
0
Exit Stop Mode
FOSCE
by Interrupt
No Delay
1
1
Freescale Semiconductor
OPTM
Bit 0
0
1.3 Mask

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