mc68hc08az60 Freescale Semiconductor, Inc, mc68hc08az60 Datasheet - Page 421

• Manufacturer Part Number: mc68hc08az60
• Description: M68hc08 Family Of 8-bit Microcontroller Units Mcus
• Manufacturer: Freescale Semiconductor, Inc

1-appA
MOTOROLA
EEPROM Timebase Divider Control Registers
NOTE:
The following are proposed register addresses. Writing to them in
current software will have no effect.
To program or erase the EEPROM content, the EEPROM control
hardware requires a constant timebase of 35 s to drive its internal timer.
EEPROM Timebase Divider EEDIV is a clock-divider which divides the
selected reference clock source to generate this constant timebase. The
reference clock input of the EEDIV is driven by either the CGMXCLK or
the system bus clock. The selection of this reference clock is defined by
the EEDIVCLK bit in the Configuration Register.
EEPROM Timebase Divider EEDIV are defined by two registers
(EEDIVH and EEDIVL) and must be programmed with a proper value
before starting any EEPROM erase/program steps. EEDIV registers
must be re-programmed when ever its reference clock is changed. The
EEDIV value can be either pre-programmed in the EEDIVHNVR and
EEDIVLNVR non-volatide memory registers, (which upon reset will load
their contents into the EEDIVH and EEDIVL registers,) or programmed
directly by software into the EEDIVH and EEDIVL registers at system
initialization . The function of the divider is to provide a constant clock
source with a period of 35 s (better be within ± 2ms) to the internal timer
and related EEPROM circuits for proper program/erase operations. The
recommended frequency range of the reference clock is 250KHz to
32MHz.
Freescale Semiconductor, Inc.
Appendix A: Future EEPROM Registers
Appendix A: Future EEPROM Registers
For More Information On This Product,
Appendix A: Future EEPROM Registers
Go to: www.freescale.com
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