mpc8544e Freescale Semiconductor, Inc, mpc8544e Datasheet

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... SPE APU. © 2010 Freescale Semiconductor, Inc. Freescale Confidential Proprietary Preliminary—Subject to Change Without Notice Document Number: MPC8544EEC Rev. 4, 09/2010 Contents 1. MPC8544E Overview . . . . . . . . . . . . . . . . . . . . . . . . . .1 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . .8 3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .13 4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . .16 6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . .16 7 ...

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... Four outbound windows plus default translation for PCI and PCI Express • DDR/DDR2 memory controller — Programmable timing supporting DDR and DDR2 SDRAM — 64-bit data interface MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Confidential Proprietary Preliminary—Subject to Change Without Notice Freescale Semiconductor ...

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... RSA and Diffie-Hellman; programmable field size up to 2048 bits – Elliptic curve cryptography with F 511 bits — DEU—Data Encryption Standard execution unit – DES, 3DES MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor m and F(p) modes and programmable field size Freescale Confidential Proprietary Preliminary— ...

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... Eight chip selects support eight external slaves — eight-beat burst transfers — The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller. — Two protocol engines available on a per chip select basis: MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev addressing mode Freescale Confidential Proprietary Preliminary— ...

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... Exact match on primary and virtual 48-bit unicast addresses – VRRP and HSRP support for seamless router fail-over – exact-match MAC addresses supported MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Freescale Confidential Proprietary Preliminary—Subject to Change Without Notice ...

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... Memory prefetching of PCI read accesses — Supports posting of processor-to-PCI and PCI-to-memory writes — PCI 3.3-V compatible — Selectable hardware-enforced coherency MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Confidential Proprietary Preliminary—Subject to Change Without Notice Freescale Semiconductor ...

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... Supports continuous bit streaming of entire block for fast upload and download • IEEE Std 1149.1™-compliant, JTAG boundary scan • 783 FC-PBGA package MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Freescale Confidential Proprietary Preliminary—Subject to Change Without Notice MPC8544E Overview ...

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... Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8544E. This device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. ...

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... Table 2. Recommended Operating Conditions Characteristic Core supply voltage PLL supply voltage Core power supply for SerDes transceivers Pad power supply for SerDes transceivers DDR and DDR2 DRAM I/O voltage MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 1 Symbol (eTSEC1) ...

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... Caution: T/LV must not exceed power-on reset and power-down sequences. 5. Caution: BV must not exceed BV IN power-on reset and power-down sequences. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol (eTSEC1) (eTSEC3 and JTAG signals Section 21.2, “ ...

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... Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8544E. B/G/L/OV DD B/G/L/OV B/G/L/ GND – 0 GND – 0.7 V Notes refers to the clock period associated with the respective interface: CLOCK 2 For I C and JTAG, t For DDR, t CLOCK For eTSEC, t For LBIU, t CLOCK ...

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... From a system standpoint, if any of the I/O power supplies ramp prior to the V associated with that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the device. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Table 3. Output Drive Capability ...

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... Section 4.2, “Real-Time Clock Timing” • Section 4.3, “eTSEC Gigabit Reference Clock Timing” • Section 4.4, “Platform to FIFO Restrictions” • Section 4.5, “Other Input Clocks” MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Table 4. Table 4. MPC8544ECore Power Dissipation Platform Frequency V ...

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... MPC8544E input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns, and the MPC8544E is compatible with spread spectrum sources if the recommendations listed in Table 6 are observed ...

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... FIFO TX/RX clock frequency ≤ platform clock frequency ÷ 3.2 For example, if the platform frequency is 533 MHz, the FIFO Tx/Rx clock frequency should be no more than 167 MHz. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor , and minimum clock low time is 2 × t ...

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... Input hold time for all POR configs (including PLL config) with respect to negation of HRESET Maximum valid-to-high impedance time for actively driven POR configs with respect to negation of HRESET Note: 1. SYSCLK is the primary clock input for the MPC8544E. Table 9 provides the PLL lock times. Parameter/Condition Core and platform PLL lock times ...

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... DDR SDRAM component(s) when GV (typ Table 12. DDR SDRAM DC Electrical Characteristics for GV Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor . Symbol Min GV 1.71 DD 0.49 × REF V ...

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... Table 15 provides the input AC timing specifications for the DDR SDRAM when GV Table 15. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface At recommended operating conditions. Parameter AC input low voltage AC input high voltage MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol Min I – – ...

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... See Figure CISKEW 3. Maximum DDR1 frequency is 400 MHz. Figure 3 shows the DDR SDRAM input timing diagram. MCK[n] MCK[n] MDQS[n] MDQ[x] Figure 3. DDR SDRAM Input Timing Diagram (t MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Min V — 0.31 IH ...

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... MCS[n] output setup with respect to MCK MCS[n] output hold with respect to MCK MCK to MDQS Skew MDQ/MECC/MDM output setup with respect to MDQS MDQ/MECC/MDM output hold with respect to MDQS MDQS preamble MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol Min t 3.75 MCK ...

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... CLK_CNTL register. The timing parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the MPC8544E PowerQUICC III Integrated Communications Processor Reference Manual, for a description and understanding of the timing modifications enabled by use of these bits. ...

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... DC electrical characteristics for the DUART interface. Table 19. DUART DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current ( High-level output voltage (OV = min MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev MCK DDKHAS DDKHCS DDKHAX DDKHCX NOOP t ...

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... Gigabit Media-Independent Interface (RGMII) Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII Consortium RMII Specification Version 1.2 (3/20/1998). The SGMII interfaces follow the Serial Gigabit Media-Independent Interface (SGMII) Specification Version 1.8. The electrical MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management ...

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... DD 3. The symbol this case, represents the LV IN MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Section 9, “Ethernet Management Interface Electrical Table 22. The potential applied to the input of a GMII, MII, TBI, RTBI, into a GMII receiver powered from a 2.5-V supply). Tolerance ...

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... V DD_SRDS2 Output high voltage V Output low voltage Output ringing V MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management 7, where C is the external (on board) AC-coupled capacitor. Each output TX Figure as long as such termination does not violate 8 ...

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... XMITEQCD (for SerDes 2 lane OD 2 and 3) bit field of MPC8544E SerDes 2 control register 1: •The MSbit (bit 0) of the above bit field is set to zero (selecting the full V •The LSbits (bit [1:3]) of the above bit field is set based on the equalization setting shown in this table. ...

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... Figure 8. SGMII Transmitter DC Measurement Circuit Table 25 shows the DC receiver electrical characteristics. Table 25. DC Receiver Electrical Characteristics Parameter Supply Voltage DC input voltage range MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management SD2_TXn 50 Ω SD_RXm Ω ...

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... The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. Refer to Section 17.4.3, “Differential Receiver (RX) Input Specifications,” 4. The LSTS shown in this table refers to the LSTSCD bit field of MPC8544E SerDes 2 control register also referred to as peak-to-peak AC common mode voltage. ...

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... The external AC coupling capacitor is required. It’s recommended to be placed near the device transmitter outputs. Vrx_diffpp_max/2 Vrx_diffpp_min/2 –Vrx_diffpp_min/2 –Vrx_diffpp_max/2 MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 9 shows the SGMII receiver input compliance mask ...

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... Table 28. FIFO Mode Transmit AC Timing Specification At recommended operating conditions with L/TVDD of 3.3 V ± 2.5 V ± 5% Parameter/Condition TX_CLK, GTX_CLK clock period TX_CLK, GTX_CLK duty cycle TX_CLK, GTX_CLK peak-to-peak jitter Rise time TX_CLK (20%–80%) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Pin Pin ...

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... FITH TXD[7:0] TX_EN TX_ER Figure 11. FIFO Transmit AC Timing Diagram RX_CLK t FIRH RXD[7:0] RX_DV RX_ER Figure 12. FIFO Receive AC Timing Diagram MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management Symbol Min t — FITF t 0.5 FITDX Symbol ...

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... GTX_CLK Min setup time is a function of clock period and max hold time (Min setup = cycle time – Max GTKHDV delay). Figure 13 shows the GMII transmit AC timing diagram. GTX_CLK TXD[7:0] TX_EN TX_ER Figure 13. GMII Transmit AC Timing Diagram MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol t GTX t GTKHDX t GTXR ...

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... GMII receive AC timing diagram. RX_CLK RXD[7:0] RX_DV RX_ER 8.6 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management 1 Symbol t GRX t ...

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... Table 33. MII Receive AC Timing Specifications At recommended operating conditions with L/TVDD of 3.3 V ± 5%.or 2.5 V ± 5%. Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev 3.3 V ± 2.5 V ± Symbol ...

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... MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER 8.7 TBI AC Timing Specifications This section describes the TBI transmit and receive AC timing specifications. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management 1 Symbol Min t 10.0 ...

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... TBI Receive AC Timing Specifications Table 35 provides the TBI receive AC timing specifications. Table 35. TBI Receive AC Timing Specifications At recommended operating conditions with L/TVDD of 3.3 V ± 2.5 V ± 5%. Parameter/Condition PMA_RX_CLK[0:1] clock period PMA_RX_CLK[0:1] skew MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol Min t — GTX t 0 ...

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... TSECn_RX_CLK pin (no receive clock is used on TSECn_TX_CLK in this mode, whereas for the dual-clock mode this is the PMA1 receive clock). The 125-MHz transmit clock is applied on the TSEC_GTX_CLK125 pin in all TBI modes. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management ...

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... Table 37. RGMII and RTBI AC Timing Specifications At recommended operating conditions with L/TV Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Clock period duration Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%–80%) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol Min t 7.5 TRR t ...

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... TX_CTL TX_CLK (At PHY) GTX_CLK (At Receiver) RXD[8:5][3:0] RXD[7:4][3:0] RX_CTL RX_CLK (At PHY) Figure 22. RGMII and RTBI AC Timing and Multiplexing Diagrams MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management of 2.5 V ± 5 Symbol Min t — RGTF represents the TBI (T) receive (RX) clock ...

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... R (rise (fall). Figure 23 shows the RMII transmit AC timing diagram. REF_CLK TXD[1:0] TX_EN TX_ER Figure 23. RMII Transmit AC Timing Diagram MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Table 38. of 3.3 V ± 2.5 V ± 5 Symbol Min t 15 ...

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... Figure 24 provides the AC test load for eTSEC. Output Figure 25 shows the RMII receive AC timing diagram. REF_CLK RXD[1:0] CRS_DV RX_ER MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management of 3.3 V ± 5%.or 2.5 V ± 5 Symbol Min t 15 ...

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... Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev “Section 8, “Enhanced Three-Speed Ethernet Table 40. Symbol –1.0 mA) ...

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... Figure 26 shows the MII management AC timing diagram. MDC MDIO (Input) MDIO (Output) Figure 26. MII Management Interface Timing Diagram MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Ethernet Management Interface Electrical Characteristics is 3.3 V ± 5 Symbol Min t — ...

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... DC electrical characteristics for the local bus interface operating 1.8 V DC. DD Table 44. Local Bus DC Electrical Characteristics (1.8 V DC) Parameter High-level input voltage Low-level input voltage Input current ( MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol –2 mA) V ...

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... Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Section 19.1, “ ...

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... Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol t ...

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... Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Local bus clock to output high Impedance (except LAD/LDP and LALE) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor DD 1 Symbol t ...

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... Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at BV /2. DD Figure 27 provides the AC test load for the local bus. Output MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol t LBKHOZ2 (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...

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... Input hold from local bus clock (except LUPWAIT) LUPWAIT input hold from local bus clock LALE output transition to LAD/LDP output transition (LATCH hold time) Local bus clock to output valid (except LAD/LDP and LALE) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor t LBIVKH1 t ...

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... LALE and any change in LAD. LBOTOT 7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol ...

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... In PLL bypass mode, LCLK[n] is the inverted version of the internal clock with the delay of t edge of the internal clock and are captured at falling edge of the internal clock withe the exception of LGTA/LUPWAIT (which is captured on the rising edge of the internal clock). MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor t LBKHKT t ...

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... GPCM Mode Input Signal: LGTA UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 30. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKHOV1 LBKHOZ1 t LBIVKH2 t ...

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... Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 31. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Bypass Mode) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor t LBKLOV1 Freescale Confidential Proprietary Preliminary—Subject to Change Without Notice ...

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... LGTA UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 32. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKHOV1 LBKHOZ1 t LBIVKH2 ...

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... Figure 33. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Bypass Mode) 11 Programmable Interrupt Controller In IRQ edge trigger mode, when an external interrupt signal is asserted (according to the programmed polarity), it must remain the assertion for at least 3 system clocks (SYSCLK periods). MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor t LBKLOV1 Freescale Confidential Proprietary Preliminary— ...

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... JTAG external clock cycle time JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Input hold times: Valid times: Output hold times: MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol ...

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... Figure 34. AC Test Load for the JTAG Interface Figure 35 provides the JTAG clock input timing diagram. JTAG External Clock Figure 35. JTAG Clock Input Timing Diagram Figure 36 provides the TRST timing diagram. TRST MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Table 3). 2 Symbol Boundary-scan data t JTKLDZ ...

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... Capacitance for each I/O pin Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. Refer to the MPC8544EPowerQUICC III Integrated Communications Host Processor Reference Manual for information on the digital filter used. 3. I/O pins will obstruct the SDA and SCL lines if OV MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 ...

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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). 2. The MPC8544E provides a hold time of at least 300 ns for the SDA signal (referred to the V the undefined region of the falling edge of SCL. ...

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... I2CF t I2CL SCL t I2SXKL S 14 GPIO This section describes the DC and AC electrical specifications for the GPIO interface of the MPC8544E. 14.1 GPIO DC Electrical Characteristics Table 53 provides the DC electrical characteristics for the GPIO interface. Table 53. GPIO DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage ...

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... GPIO inputs are required to be valid for at least t Figure 40 provides the AC test load for the GPIO. Output 15 PCI This section describes the DC and AC electrical specifications for the PCI bus of the MPC8544E. 15.1 PCI DC Electrical Characteristics Table 55 provides the DC electrical characteristics for the PCI interface. ...

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... PCI 2.2 Local Bus PCRHFV Specifications. 9. The reset assertion timing requirement for HRESET is 100 μs. Figure 41 provides the AC test load for PCI. Output MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev provides the PCI AC timing specifications at 66 MHz. 1 Symbol t PCKHOV ...

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... Figure 43. PCI Output AC Timing Measurement Condition 16 High-Speed Serial Interfaces (HSSI) The MPC8544E features two serializer/deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications.The SerDes1 dedicated for PCI Express data transfers. The SerDes2 can be used for PCI Express and/or SGMII application. This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes Reference Clocks. The SerDes data lane’ ...

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... Sometimes, it may be even different between the receiver input and driver output circuits within the same component also referred as the DC offset in some occasions. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev (or Differential Output Swing): OD – ...

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... Figure 45. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50-Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling. — The external reference clock driver must be able to drive this termination. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Differential Swing ...

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... SDn_REF_CLK Figure 45. Receiver of SerDes Reference Clocks 16.2.2 DC Level Requirement for SerDes Reference Clocks The DC level requirement for the MPC8544E SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below. • ...

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... Figure 46. Differential Reference Clock Input DC Requirements (External DC-Coupled) 200 mV < Input Amplitude or Differential Peak < 800 mV SDn_REF_CLK SDn_REF_CLK Figure 47. Differential Reference Clock Input DC Requirements (External AC-Coupled) MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Figure 47 Freescale Confidential Proprietary Preliminary—Subject to Change Without Notice High-Speed Serial Interfaces (HSSI) Section 16.2.1, “ ...

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... The system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the MPC8544E SerDes reference clock receiver requirement provided in this document. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev NOTE Figure 52 are for conceptual reference only ...

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... Figure 49 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with MPC8544E SerDes reference clock input’s DC requirement. HCSL CLK Driver Chip CLK_Out 33 Ω Clock Driver Clock Driver 33 Ω ...

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... Figure 51. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only) Figure 52 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with MPC8544E SerDes reference clock input’s DC requirement. Single-Ended CLK Driver Chip 33 Ω ...

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... Rise Edge Rage V = +200 –200 mV IL SDn_REF_CLK minus SDn_REF_CLK Figure 53. Differential Measurement Points for Rise and Fall Time MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Rise Edge Rate Fall Edge Rate Rise-Fall Matching Figure 53. ...

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... Section 8.3, “SGMII Interface Electrical Characteristics” • Section 17, “PCI Express” Please note that external AC Coupling capacitor is required for the above serial transmission protocols with the capacitor value defined in specification of each protocol section. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev SDn_REF_CLK V + 100 mV ...

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... The following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well as the specifications of the transport and data link layer please refer to the PCI Express Base Specification. Rev. 1.0a. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Min — ...

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... IDLE-DELTA during LO and electrical idle V Absolute delta of DC TX-CM-DC-LINE-DELTA common mode between D+ and D– V Electrical idle TX-IDLE-DIFFp differential peak output voltage MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Min Nom Max Unit 399.88 400 400.12 0.8 — 1.2 –3.0 –3.5 – ...

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... Common mode return TX-CM loss Z DC differential TX TX-DIFF-DC impedance Z Transmitter DC TX-DC impedance L Lane-to-lane output TX-SKEW skew C AC coupling capacitor TX MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Min Nom Max Unit — — 600 0 — 3.6 — — — — ...

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... TX UI recommended that the recovered calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function (that is, least squares and median deviation fits). MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Min Nom Max ...

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... Parameter UI Unit interval V Differential peak-to- RX-DIFFp-p peak input voltage T Minimum receiver RX-EYE eye width MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor [Transition Bit 800 mV TX-DIFFp-p-MIN [De-Emphasized Bit] 566 mV (3 dB) >= V >= 505 mV (4 dB) TX-DIFFp-p-MIN 0. – 0 ...

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... RX-DC Z Powered down DC RX-HIGH-IMP-DC input impedance V Electrical idle detect RX-IDLE-DET-DIFFp-p threshold T Unexpected RX-IDLE-DET-DIFF- electrical idle enter ENTERTIME detect threshold integration time MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Min Nom Max Units — — 0.3 UI — — 150 mV 15 — — ...

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... RX package and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Min ...

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... D+ and D– not being exactly matched in length at the package pin boundary. D+ Package D+ Package D– Package Figure 58. Compliance Test/Measurement Load MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev NOTE Figure 57). Note that the series capacitors, CTX, are V > 175 mV RX-DIFFp-p-MIN 0 ...

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... The package parameters for flip chip plastic ball grid array (FC-PBGA) are provided in Package outline Interconnects Ball pitch Ball diameter (typical) Solder ball (Pb-free) Note: 1. (FC-PBGA) without a lid. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Table 61. Package Parameters Parameter PBGA 29 mm × 783 1 mm ...

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... Package Description 18.2 Mechanical Dimensions of the MPC8544E FC-PBGA Figure 59 shows the mechanical dimensions and bottom surface nomenclature of the MPC8544E, 783 FC-PBGA package without a lid. Notes: 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. ...

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... Pinout Listings Table 62 provides the pinout listing for the MPC8544E 783 FC-PBGA package. The naming convention of TSEC1 and TSEC3 is used to allow the splitting voltage rails for the eTSEC blocks and to ease the port of existing PowerQUICC III software. The DMA_DACK[0:1] and TEST_SEL pins must be set to a proper state during POR configuration ...

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... L19 LA[28:31] K16, K17, H17,G17 LCS[0:4] K18, G19, H19, H20, G16 LCS5/DMA_DREQ2 H16 MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Package Pin Number DDR SDRAM Memory Interface Local Bus Controller Interface Freescale Confidential Proprietary Preliminary—Subject to Change Without Notice Power ...

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... AC19 IRQ[9]/DMA_DREQ3 AG20 IRQ[10]/DMA_DACK3 AE27 IRQ[11]/DMA_DDONE3 AE24 IRQ_OUT AD14 MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number DMA Programmable Interrupt Controller Freescale Confidential Proprietary Preliminary—Subject to Change Without Notice Package Description Power Pin Type ...

Page 86

... TSEC3_TX_CLK L10 TSEC3_TX_EN N6 TSEC3_TX_ER L8 UART_CTS[0:1] AH8, AF6 UART_RTS[0:1] AG8, AG9 MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Package Pin Number Ethernet Management Interface Gigabit Reference Clock DUART Freescale Confidential Proprietary Preliminary—Subject to Change Without Notice Power Pin Type Notes ...

Page 87

... SD2_TX[3] AA5 SD2_TX[0] AA20 SD2_TX[2] AB4 SD2_TX[3] Y5 SD2_PLL_TPD AG3 SD2_REF_CLK AE2 MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number interface SerDes 1 SerDes 2 Freescale Confidential Proprietary Preliminary—Subject to Change Without Notice Package Description Power Pin Type ...

Page 88

... AH16 TCK AG28 TDI AH28 TDO AF28 TMS AH27 TRST AH22 MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Package Pin Number General-Purpose Output General-Purpose Input System Control Debug Clock JTAG Freescale Confidential Proprietary Preliminary—Subject to Change Without Notice Power ...

Page 89

... E2, E8,C24, E18, F5, E14, C21, G3, G7, G9, G11, H5, H12, E22, F15, J10, K3, K12, K14, H14, D20, E11, M1 L23, J18, J19, F20, F23, H26, J21, J23 DD MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number DFT Thermal Management Power Management ...

Page 90

... AE3, AE1, AE25, AF3, AH2 AGND_SRDS2 AF1 AVDD_LBIU C28 AVDD_PCI1 AH20 AVDD_CORE AH14 AVDD_PLAT AH18 MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Package Pin Number Freescale Confidential Proprietary Preliminary—Subject to Change Without Notice Power Pin Type Supply Power for core ...

Page 91

... Thus, no external pull-down resistor is needed for selecting the default configuration value. 5. Treat these pins as no connects (NC) unless using debug address functionality. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number Analog Signals ...

Page 92

... These pins are used for automatic calibration of the DDR IOs. 26.For SGMII mode. 27.Connect to GND. 28.For systems that boot from a local bus (GPCM)-controlled flash, a pull-up on LGPL4 is required. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Package Pin Number Section 19.3, “e500 Core PLL Ratio.” ...

Page 93

... Clocking This section describes the PLL configuration of the MPC8544E. Note that the platform clock is identical to the core complex bus (CCB) clock. 19.1 Clock Ranges Table 63 provides the clocking specifications for the processor cores and specifications for the memory bus. Table 63. Processor Core Clocking Specifications ...

Page 94

... The use of PCI_CLK is optional if SYSCLK is in the range of 33–66 MHz. If SYSCLK is outside this range then use of PCI_CLK is required as a separate PCI clock source, asynchronous with respect to SYSCLK. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev Table 65. CCB Clock Ratio ...

Page 95

... Table 68. Frequency Options of SYSCLK with Respect to Memory Bus Speeds CCB to SYSCLK Ratio 33. 333 12 400 16 533 MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Table 67. SEC Frequency Ratio Value (Binary SYSCLK (MHz) 41.66 66.66 83 Platform /CCB Frequency (MHz) — 333 333 415 400 ...

Page 96

... Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method (MIL SPEC-883 Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1°C/W. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev for additional information ...

Page 97

... Simulations with heat sinks were done with the package mounted on the 2s2p thermal test board. The thermal interface material was a typical thermal grease such as Dow Corning 340 or Wakefield 120 grease. For system thermal modeling, the MPC8544E thermal model without a lid is shown in substrate is modeled as a block 29 × 29 × 1.18 mm with an in-plane conductivity of 18.0 W/m•K and a through-plane conductivity of 1.0 W/m• ...

Page 98

... A Top View Figure 60. System Level Thermal Model for MPC8544E (Not to Scale) The Flotherm library files of the parts have a dense grid to accurately capture the laminar boundary layer for flow over the part in standard JEDEC environments, as well as the heat spreading in the board under the package ...

Page 99

... This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and thermal interface material. The MPC8544E implements several features designed to assist with thermal management, including the temperature diode. The temperature diode allows an external device to monitor the die temperature in order to detect excessive temperature conditions and alert the system ...

Page 100

... Several heat sinks offered by Aavid Thermalloy, Advanced Thermal Solutions, Alpha Novatech, IERC, Chip Coolers, Millennium Electronics, and Wakefield Engineering offer different heat sink-to-ambient thermal resistances, that will allow the MPC8544E to function in various environments. 20.3.1 Internal Package Conduction Resistance ...

Page 101

... As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. The bare joint results in a thermal resistance approximately six times greater than the thermal grease joint. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Radiation ...

Page 102

... Internet: www.dow.com Shin-Etsu MicroSi, Inc.888-642-7674 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company800-347-4572 th 18930 West 78 St. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 102 Contact Pressure (psi) Freescale Confidential Proprietary Preliminary—Subject to Change Without Notice Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0 ...

Page 103

... Assuming an air velocity of 1 m/s, we have an effective θ = 30° + 5°C + (0.1°C/W + 1.0°C/W + 5°C/W) × resulting in a die-junction temperature of approximately 66, which is well within the maximum operating temperature of the component. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor + θ + θ ) × ...

Page 104

... Temperature Diode The MPC8544E has a temperature diode on the microprocessor that can be used in conjunction with other system temperature monitoring devices (such as Analog Devices, ADT7461™). These devices use the negative temperature coefficient of a diode operated at a constant current to determine the temperature of the microprocessor and its environment recommended that each device be individually calibrated. ...

Page 105

... The PCI PLL generates the clocking for the PCI bus. • The local bus PLL generates the clock for the local bus. • There are two PLLs for the SerDes block. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor is flowing H is flowing L – ...

Page 106

... All traces should be kept short, wide, and direct Note 0805 sized capacitor is recommended for system initial bring-up. Figure 66. SerDes PLL Power Supply Filter Circuit MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 106 _PCI, AV _LBIU, and and preferably these voltages will be derived directly from Ω ...

Page 107

... This noise must be prevented from reaching other components in the MPC8544E system, and the device itself requires a clean, tightly regulated source of power. Therefore recommended that the system designer place at least one decoupling capacitor at each V of the device ...

Page 108

... GND pins of the device 21.6 Pull-Up and Pull-Down Resistor Requirements The MPC8544E requires weak pull-up resistors (2–10 kΩ is recommended) on open drain type pins 2 including I C pins and MPIC interrupt pins. Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 69 ...

Page 109

... Configuration Pin Muxing The MPC8544E provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. ...

Page 110

... IC). Regardless of the numbering, the signal placement recommended in all known emulators. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 110 Figure 68, for connection to the target system, and is Freescale Confidential Proprietary Preliminary— ...

Page 111

... JTAG interface may need to be wired onto the system in future debug situations. • No pull-up/pull-down is required for TDI, TMS, or TDO. Figure 68 shows the COP connector physical pinout. COP_RUN/STOP COP_SRESET COP_HRESET COP_CHKSTP_OUT MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor COP_TDO NC COP_TDI 3 ...

Page 112

... This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to position B. 6. Asserting SRESET causes a machine check interrupt to the e500 core. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 112 COP_HRESET COP_SRESET ...

Page 113

... All PCI control pins can be grouped together and tied to OV • optional to disable PCI block through DEVDISR register after POR reset. MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Freescale Confidential Proprietary Preliminary—Subject to Change Without Notice System Design Information through a single 10-kΩ ...

Page 114

... Contact your local Freescale sales office or regional marketing team for order information. 22.1 Industrial and Commercial Tier Qualification The MPC8544E device has been tested to meet the industrial tier qualification. description for commercial and industrial qualifications. Table 74. Commercial and Industrial Description Typical Application ...

Page 115

... MMMMM is the 5-digit mask number. ATWLYYWW is the traceability code. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. Figure 70. Part Marking for FC-PBGA Device MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Table 75. Device Nomenclature C ...

Page 116

... Document Revision History 23 Document Revision History Table 76 provides a revision history for the MPC8544E hardware specification. Table 76. MPC8544E Document Revision History Revision Date 4 09/2010 • Modified local bus information in as 133 MHz. • Added footnote 28 to • Updated solder-ball parameter in 3 11/2009 • ...

Page 117

... Freescale Semiconductor Literature Distribution Center 1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8544EEC Rev. 4 09/2010 Freescale Confidential Proprietary Preliminary—Subject to Change Without Notice Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...