mpc8544e Freescale Semiconductor, Inc, mpc8544e Datasheet - Page 31

• Manufacturer Part Number: mpc8544e
• Description: Mpc8544e Powerquicc Iii Integrated Processor
• Manufacturer: Freescale Semiconductor, Inc

Timing diagrams for FIFO appear in
Freescale Semiconductor
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
(continued)At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
Fall time TX_CLK (80%–20%)
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN
hold time
Note:
1. Data valid t
RX_CLK clock period
RX_CLK duty cycle
RX_CLK peak-to-peak jitter
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RX_CLK to RXD[7:0], RX_DV, RX_ER hold time
(Min setup = Cycle time – Max hold).
GTX_CLK
RXD[7:0]
RX_CLK
TXD[7:0]
FITDV
RX_ER
RX_DV
Parameter/Condition
Parameter/Condition
TX_EN
TX_ER
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
to GTX_CLK Min setup time is a function of clock period and max hold time.
Table 28. FIFO Mode Transmit AC Timing Specification (continued)
Table 29. FIFO Mode Receive AC Timing Specification
t
t
FIRH
FITH
Figure 11. FIFO Transmit AC Timing Diagram
Figure 12. FIFO Receive AC Timing Diagram
Preliminary—Subject to Change Without Notice
t
t
t
FIR
FIRDV
FIT
t
FITDV
Figure 11
Freescale Confidential Proprietary
t
FIRH
Valid Data
Symbol
Symbol
t
t
t
and
t
FIRDX
FITDX
t
FIRDV
t
t
FIRR
t
FIRF
FITF
FIRJ
FIR
/t
FIRH
Figure
Enhanced Three-Speed Ethernet (eTSEC), MII Management
t
12.
FITDX
Min
Min
0.5
1.5
0.5
45
—
—
—
—
—
t
FIRDX
Typ
Typ
8.0
50
—
—
—
—
—
—
—
t
t
FITF
FIRF
Max
0.75
Max
0.75
0.75
250
3.0
55
—
—
—
t
FITR
t
FIRR
Unit
Unit
ns
ns
ns
ps
ns
ns
ns
ns
%
Notes
Notes
—
—
—
—
—
—
—
1
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