lm4550 National Semiconductor Corporation, lm4550 Datasheet - Page 18

• Manufacturer Part Number: lm4550
• Description: Ac ?97 Rev 2.1 Multi-channel Audio Codec With Stereo Headphone Amplifier, Sample Rate Conversion And National 3d Sound
• Manufacturer: National Semiconductor Corporation

www.national.com
Application Information
AC Link Input Frame: SDATA_IN (input to controller,
output from LM4550)
The audio input frame (input to the AC ’97 Digital Controller)
contains status and PCM data from the LM4550 control
registers and stereo ADC. The Tag slot, slot 0, contains 16
bits that tell the AC ’97 Digital Controller whether the LM4550
is ready and the validity of data from certain device subsec-
tions.
A new audio input frame is signaled with a low to high
transition of SYNC. SYNC is synchronous to the rising edge
of BIT_CLK. On the next rising edge of BIT_CLK, the
LM4550 drives SDATA_IN with the first bit of slot 0. The
Digital Controller samples SDATA_IN on the falling edge of
BIT_CLK. The LM4550 will continue outputting the
SDATA_IN stream on each successive rising edge of BIT-
_CLK. The LM4550 outputs data MSB first, in a MSB justi-
fied format. All reserved bits and slots are stuffed with "0" ’s
by the LM4550.
SDATA_IN Slot 0: Codec Status Bits
The first bit of SDATA_IN Slot 0 (bit 15) indicates when the
Codec is ready. The digital controller must probe further to
see which other subsections are ready.
SDATA_IN Slot 1: Status Address / Slot Request Bits
This slot echoes the control register which a read was re-
quested on. The address echoed was initiated by a read
request in the previous SDATA_OUT frame, slot 1. Bits 11
and 10 are slot request bits that support Sample Rate Con-
version (SRC) functionality. If bit 11 is set to 0, then the
controller should respond with a valid PCM left sample in slot
3 of the next frame. If bit 10 is set to 0, then the controller
Bit
15
14
13
12
11
FIGURE 7. Start of Audio Input Frame
Codec Ready
Description
Slot 1 data
Slot 2 data
Slot 3 data
Slot 4 data
valid
valid
valid
valid
Bit
Right Audio PCM Data is
0=Not Ready, 1=Ready
Left Audio PCM Data is
Status Address is valid
Status Data is valid
Comment
valid
valid
(Continued)
10097207
18
should respond with a valid PCM right sample in slot 4 of the
next frame. If bits 11 or 10 are set to 1, the controller should
not send data in the next frame. Bits 9, 4, 3, and 2 are
unused. Bits 1 and 0 are reserved and should be set to 0.
SDATA_IN Slot 2: Status Data
The slot returns the control register data. The data returned
was initiated by a read request in the previous SDATA_OUT
frame, slot 1.
18:12
19:4
Bits
Bits
4:2
1,0
3:0
19
10
11
9
8
7
6
5
Slot 7 Request
bit (PCM Left
Surround)
Slot 8 Request
bit (PCMRight
Surround)
Slot 9 Request
bit (PCM LFE)
Slot 3 Request
Slot 4 Request
bit (PCM right)
Slot 5 Request
Slot 6 Request
Register Index
Register Read
bit (PCM left)
Request bits
Description
Description
Other Slot
Reserved
Reserved
Reserved
bit (PCM
Center)
Control
Control
Data
bit
0 = Controller should send
valid slot 9 data in the next
frame, 1 = Controller
should not send slot 9 data
in the next frame
valid slot 3 data in the next
should not send slot 3 data
valid slot 4 data in the next
should not send slot 4 data
valid slot 6 data in the next
should not send slot 6 data
valid slot 7 data in the next
should not send slot 7 data
valid slot 8 data in the next
should not send slot 8 data
0 = Controller should send
0 = Controller should send
0 = Controller should send
0 = Controller should send
0 = Controller should send
Echo of Control Register
for which data is being
Unused - Stuff with "0"
Unused - stuff with "0"
frame, 1 = Controller
frame, 1 = Controller
frame, 1 = Controller
frame, 1 = Controller
frame, 1 = Controller
Stuffed with "0" ’s
in the next frame
in the next frame
in the next frame
in the next frame
in the next frame
Stuffed with "0"
Stuff with "0"
Comment
Comment
returned.