lm4550 National Semiconductor Corporation, lm4550 Datasheet - Page 19

• Manufacturer Part Number: lm4550
• Description: Ac ?97 Rev 2.1 Multi-channel Audio Codec With Stereo Headphone Amplifier, Sample Rate Conversion And National 3d Sound
• Manufacturer: National Semiconductor Corporation

Application Information
SDATA_IN Slot 3: PCM Record Left Channel
This slot contains the left ADC sample data. The signal to be
digitized is selected via register 1Ah and subsequently
routed through the Input Mux for recording by the left ADC.
This is a 20-bit slot, where the digitized 18-bit PCM data is
output from the codec MSB first and the last remaining 2 bits
will zeros.
SDATA_IN Slot 4: PCM Record Right Channel
This slot contains the right ADC sample data. The signal
digitized is selected via register 1Ah and subsequently
routed through the Input Mux for recording by the right ADC.
Register Descriptions
Reset Register (00h)
Writing any value to this register causes a register reset
which changes all of the registers back to their default val-
ues. If a read is performed on this register, the LM4550 will
return a value of 0D50h indicating that National 3D Sound is
implemented, 18bit data is supported for both the ADC’s and
DAC’s, and the volume control for True Line Level Out is
supported.
Master Volume Registers (02h, 06h)
These registers allow the output levels from LINE_OUT and
MONO_OUT to be attenuated or muted. There are 6-bits of
volume control, plus one mute bit. It is a 5-bit volume range,
where each step is nominally 1.5dB and each output can be
individually muted by either setting the most significant bit
(Mx4), and/or the mute bit (D15) to "1."
Bits
19:2
1:0
PCM Record
Left Channel
Description
Reserved
data
18 bit audio sample from
Stuffed with "0"’s
Comment
left ADC
(Continued)
FIGURE 8. AC Link Powerdown Timing
19
This is a 20-bit slot, where the digitized 18-bit PCM data is
output from the codec MSB first and the last remaining 2 bits
will zeros.
SDATA_IN Slots 5-12: Reserved
These SDATA_IN slots are set to "0" as they are reserved for
future use.
AC Link Low Power Mode
Headphone Volume Registers (04h)
This registers allows the output levels from the HP_OUT to
be attenuated or muted. There are 6-bits of volume control,
plus one mute bit. It is a 5-bit volume range, where each step
is nominally 1.5dB and each output can be individually
muted by either setting the most significant bit (Mx4), and/or
the mute bit (D15) to "1."
PC Beep Register (0Ah)
This register controls the level of the PC_BEEP input. The
PC_BEEP can be both attenuated and muted via register
0Ah. Step size is nominally 3dB. The signal present after the
attenuation and mute block is summed into both the left and
Default: 8000h
Mute
Bits
19:2
1:0
0
0
1
Right Channel
PCM Record
Description
Reserved
Mx4:Mx0
X XXXX
0 0000
1 1111
data
18 bit audio sample from
46.5dB attenuation
Stuffed with "0"’s
0dB attenuation
Comment
right ADC
Function
mute
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