sc18is602b NXP Semiconductors, sc18is602b Datasheet
sc18is602b
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sc18is602b Summary of contents
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... C-bus to SPI bridge Rev. 5 — 3 August 2010 1. General description The SC18IS602B is designed to serve as an interface between a standard I microcontroller and an SPI bus. This allows the microcontroller to communicate directly with SPI devices through its I slave-transmitter or slave-receiver and an SPI master. The SC18IS602B controls all the SPI bus-specific sequences, protocol, and timing ...
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... I C-BUS CONTROL REGISTER SC18IS602B INTERRUPT CONTROL LOGIC Block diagram of SC18IS602B All information provided in this document is subject to legal disclaimers. Rev. 5 — 3 August 2010 SC18IS602B 2 I C-bus to SPI bridge BUFFER SPI INTERNAL OSCILLATOR ...
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... I/O SPI slave select output 3 (active LOW) or GPIO address input address input address input 2 All information provided in this document is subject to legal disclaimers. Rev. 5 — 3 August 2010 SC18IS602B 2 I C-bus to SPI bridge SS3/GPIO3 ...
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... The SC18IS602B will be a slave-receiver when the 2 I C-bus master is sending data time does the SC18IS602B act master, however, it does have the ability to hold the SCL line LOW between bytes to complete its internal processes. SC18IS602B ...
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... A message begins with the SC18IS602B address, followed by the Function ID. Depending upon the Function ID, zero to 200 data bytes can follow. The SC18IS602B will place the data received into a buffer and continue loading the buffer until a STOP condition is received. After the STOP condition is detected, further communications will not be acknowledged until the function designated by the Function ID has been completed ...
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... Read from buffer A read from the data buffer requires no Function ID. The slave address with the R/W bit set to a ‘1’ will cause the SC18IS602B to send the buffer contents to the I The buffer contents are not modified during the read process. Fig 8. ...
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... SPI Interface’ command to the I Fig 9. After the SC18IS602B address is transmitted on the bus, the Configure SPI Interface Function ID (F0h) is sent followed by a byte which will define the SPI communications. The Clock Phase bit (CPHA) allows the user to set the edges for sampling and changing data ...
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... NXP Semiconductors 7.1.6 Clear Interrupt - Function ID F1h An interrupt is generated by the SC18IS602B after any SPI transmission has been completed. This interrupt can be cleared (INT pin HIGH) by sending a ‘Clear Interrupt’ command not necessary to clear the interrupt; when polling the device, this function may be ignored ...
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... NXP Semiconductors 7.1.9 GPIO Read - Function ID F5h The state of the pins defined as GPIO may be read into the SC18IS602B data buffer using the GPIO Read function. Fig 13. GPIO Read Note that this function does not return the value of the GPIO. To receive the GPIO contents, a one-byte Read Buffer command would be required ...
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... SS1[1:0] = 10: input-only (high-impedance) SS1[1:0] = 11: open-drain SS0.1 SS0[1:0] = 00: quasi-bidirectional SS0[1:0] = 01: push-pull SS0.0 SS0[1:0] = 10: input-only (high-impedance) SS0[1:0] = 11: open-drain All information provided in this document is subject to legal disclaimers. Rev. 5 — 3 August 2010 SC18IS602B 2 I C-bus to SPI bridge SS1.1 SS1.0 SS0.1 © NXP B.V. 2010. All rights reserved. ...
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... When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the pin HIGH. The quasi-bidirectional pin configuration is shown in Although the SC18IS602B device, most of the pins are 5 V tolerant applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from the pin to V configured in quasi-bidirectional mode is discouraged ...
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... Figure P N pin latch data input data All information provided in this document is subject to legal disclaimers. Rev. 5 — 3 August 2010 SC18IS602B 2 I C-bus to SPI bridge GPIO pin glitch rejection 002aab883 17 Schmitt-triggered input that GPIO pin 002aab884 18 ...
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... Clear the interrupt. This is not required if using a polling method rather than interrupts. 4. Write the 8 data bytes. The first byte (Function ID) tells the SC18IS602B which Slave Select output to use. This example uses SS2 (shown as 04h). The first byte sent to the EEPROM is normally 02h for the EEPROM write command. The next one or two bytes represent the subaddress in the EEPROM ...
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... We would like to read back 8 bytes so we can send eight bytes of FFh to tell the SC18IS602B to send eight more bytes on MOSI. While it is sending these eight data bytes also reading the MISO pin and saving the data in the buffer. ...
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... I OH quasi-bidirectional mode logical 0 all ports all ports; logical 1-to All information provided in this document is subject to legal disclaimers. Rev. 5 — 3 August 2010 SC18IS602B 2 I C-bus to SPI bridge [1] Min Typ - 5.6 - 3.3 0.22V ...
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... SPICLKL t t SPIF SPIR t t SPICLKL SPICLKH t t SPIDSU SPIDH MSB/LSB SPIDV SPIOH master MSB/LSB out All information provided in this document is subject to legal disclaimers. Rev. 5 — 3 August 2010 SC18IS602B 2 I C-bus to SPI bridge Min Typ 7.189 - = 25 ° 125 - - - 543 - 271 ...
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... SPIDSU SPIDH MSB/LSB SPIDV SPIOH master MSB/LSB out All information provided in this document is subject to legal disclaimers. Rev. 5 — 3 August 2010 SC18IS602B 2 I C-bus to SPI bridge t SPIR LSB/MSB in t SPIDV master LSB/MSB out © NXP B.V. 2010. All rights reserved. t SPIDV ...
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... 2.5 scale (1) ( 0.30 0.2 5.1 4.5 0.65 0.19 0.1 4.9 4.3 REFERENCES JEDEC JEITA MO-153 All information provided in this document is subject to legal disclaimers. Rev. 5 — 3 August 2010 SC18IS602B detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 ...
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... Solder bath specifications, including temperature and impurities SC18IS602B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 3 August 2010 SC18IS602B 2 I C-bus to SPI bridge © NXP B.V. 2010. All rights reserved ...
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... Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 22. All information provided in this document is subject to legal disclaimers. Rev. 5 — 3 August 2010 SC18IS602B 2 I C-bus to SPI bridge Figure 22) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 ...
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... Input/Output Inter-Integrated Circuit bus Least Significant Bit Machine Model Most Significant Bit Serial Peripheral Interface All information provided in this document is subject to legal disclaimers. Rev. 5 — 3 August 2010 SC18IS602B 2 I C-bus to SPI bridge peak temperature time 001aac844 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 15. Revision history Table 17. Revision history Document ID Release date SC18IS602B v.5 20100803 • Modifications: • • • • • • • • SC18IS602_602B_603 v.4 20080311 SC18IS602_603 v.3 20070813 SC18IS602_603 v.2 20061213 SC18IS602_603 v.1 20060926 SC18IS602B Product data sheet Data sheet status Product data sheet Type number SC18IS603IPW (basic type SC18IS603) removed from data sheet. ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 5 — 3 August 2010 SC18IS602B 2 I C-bus to SPI bridge © NXP B.V. 2010. All rights reserved. ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 5 — 3 August 2010 SC18IS602B 2 I C-bus to SPI bridge © NXP B.V. 2010. All rights reserved ...
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... NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 2 I C-bus to SPI bridge All rights reserved. Date of release: 3 August 2010 Document identifier: SC18IS602B ...