sc18im700 NXP Semiconductors, sc18im700 Datasheet
sc18im700
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sc18im700 Summary of contents
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... SC18IM700 Master I Rev. 02 — 10 August 2007 1. General description The SC18IM700 is designed to serve as an interface between the standard UART port of a microcontroller or microprocessor and the serial I or microprocessor to communicate directly with other I can operate sequences, protocol, arbitration and timing. The host communicates with SC18IM700 with ASCII messages protocol ...
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... NXP Semiconductors 4. Ordering information Table 1. Type number SC18IM700IPW 5. Block diagram Fig 1. Block diagram of SC18IM700 SC18IM700_2 Product data sheet Master I Ordering information Package Name Description TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SC18IM700 RX TX UART RESET WAKEUP Rev. 02 — 10 August 2007 ...
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... I RS-232 receive input 10 O RS-232 transmit input 11 I/O programmable I/O pin 12 - power supply 13 I Wake up SC18IM700 from Power-down mode. Pulling LOW by the host to wake up the device resistor must be connected between V and this pin I/O programmable I/O pin 15 O programmable I/O pin 16 O programmable I/O pin Rev. 02 — ...
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... SC18IM700 has a time-out feature. The delay between any two bytes of data coming from the host should be less than 655 ms. If this condition is not met, the SC18IM700 will time-out and clear the receive buffer. The SC18IM700 then starts to wait for the next command from the host. ...
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... I C-bus slave. The frame is then terminated with a P character. Once the host issues this command, the SC18IM700 will access the I bytes from the addressed I Note that the second byte sent is the I bit (R) of this byte must be set indicate this Fig 4 ...
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... The host issues the internal register read command by sending an R character followed by the registers to be read. The frame is then terminated with a P character. Once the command is issued, SC18IM700 will access its internal registers and returns the contents of these registers to the host. ...
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... Fig 10. Repeated START: write after write 7.1.9 Power-down mode The SC18IM700 can be placed in a low-power mode. In this mode the internal oscillator is stopped and SC18IM700 will no longer respond to the host messages. Enter the Power-down mode by sending the power-down character Z (0x5A) followed by the two defi ...
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... C-bus interface that supports data transfers up to 400 kHz C-bus SC18IM700 2 C-bus configuration Rev. 02 — 10 August 2007 SC18IM700 2 Master I C-bus controller with UART interface Figure 12. The SC18IM700 device provides SDA SCL C-BUS I C-BUS DEVICE DEVICE 002aab801 © NXP B.V. 2007. All rights reserved ...
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Register summary Table 4. Internal registers summary Register Register Bit 7 Bit 6 address General register set 0x00 BRG0 bit 7 bit 6 0x01 BRG1 bit 7 bit 6 0x02 PortConf1 GPIO3.1 GPIO3.0 0x03 PortConf2 GPIO7.1 GPIO7.0 0x04 IOState ...
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... The SC18IM700 device, but the pins are 5 V tolerant. In quasi-bidirectional mode user applies the pin, there will be a current flowing from the pin to V extra power consumption ...
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... SS input data input data glitch rejection strong N pin latch data V SS input data glitch rejection Rev. 02 — 10 August 2007 SC18IM700 very weak weak GPIOn glitch rejection 002aac076 GPIO pin 002aab884 GPIO pin 002aab885 © NXP B.V. 2007. All rights reserved. ...
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... C-bus. The least significant bit is not used, but should 2 C-bus device address used by the bus master. 6 7.3728 10 = ------------------------------------------------------------------- - 2 I 2CClkH + I 2CClkL Rev. 02 — 10 August 2007 SC18IM700 2 Master I C-bus controller with UART interface GPIO pin V SS glitch rejection 002aab883 2 C-bus address. The most 2 ...
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... Bit 4 Bit 3 Bit Rev. 02 — 10 August 2007 SC18IM700 2 Master I C-bus controller with UART interface 2 C-bus state transition. sec onds 2 Bit 1 Bit 0 I C-bus status description 0 0 I2C_OK 0 1 I2C_NACK_ON_ADDRESS 1 0 I2C_NACK_ON_DATA 0 0 I2C_TIME_OUT © ...
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... HIGH-level output current per input/output pin GPIO3 to GPIO7 all other pins LOW-level output current per input/output pin maximum total I/O current total power dissipation per package unless otherwise noted. SS Rev. 02 — 10 August 2007 SC18IM700 2 C-bus controller with UART interface [1][2] Conditions Min 55 65 referenced to V 0.5 SS ...
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... GPIO0 to GPIO2 mA; quasi-bidirectional OH mode; all GPIOs logic 0; all ports 0 all ports logic 1-to-0; all ports 2 3 Rev. 02 — 10 August 2007 SC18IM700 2 C-bus controller with UART interface [1] Min Typ Max - 3. 0.2 0.22V 0. ...
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... Conditions LOW-level HIGH-level t t SU;DAT HD;STA SU;STA HIGH Sr t HD;DAT Rev. 02 — 10 August 2007 SC18IM700 2 C-bus controller with UART interface = 2 3 Standard mode Fast mode C-bus I C-bus Min Max Min 0 100 0 4 ...
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... Product data sheet 2.5 scale (1) ( 0.30 0.2 5.1 4.5 0.65 0.19 0.1 4.9 4.3 REFERENCES JEDEC JEITA MO-153 Rev. 02 — 10 August 2007 SC18IM700 2 Master I C-bus controller with UART interface detail 6.6 0.75 0.4 1 0.2 0.13 6.2 ...
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... Solder bath specifications, including temperature and impurities SC18IM700_2 Product data sheet 2 Master I C-bus controller with UART interface Rev. 02 — 10 August 2007 SC18IM700 © NXP B.V. 2007. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 19. Rev. 02 — 10 August 2007 SC18IM700 2 C-bus controller with UART interface Figure 19) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 ...
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... Data sheet status Product data sheet summary”: added column “Default value” Product data sheet Rev. 02 — 10 August 2007 SC18IM700 2 Master I C-bus controller with UART interface peak temperature Change notice Supersedes - SC18IM700_1 - - © NXP B.V. 2007. All rights reserved. time 001aac844 ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 10 August 2007 SC18IM700 2 C-bus controller with UART interface © NXP B.V. 2007. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com SC18IM700 All rights reserved. Date of release: 10 August 2007 Document identifier: SC18IM700_2 ...