sc18im700 NXP Semiconductors, sc18im700 Datasheet - Page 8
sc18im700
Manufacturer Part Number
sc18im700
Description
Master I-2c - Bus Controller With Uart Interface
Manufacturer
NXP Semiconductors
Datasheet
1.SC18IM700.pdf
(22 pages)
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NXP Semiconductors
8. I
SC18IM700_2
Product data sheet
2
C-bus serial interface
The I
connected to the bus, and it has the following features:
A typical I
byte-oriented I
Fig 12. I
•
•
•
•
•
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
2
C-bus uses two wires (SDA and SCL) to transfer information between devices
2
2
C-bus configuration
C-bus configuration is shown in
2
C-bus interface that supports data transfers up to 400 kHz.
I
2
C-bus
Rev. 02 — 10 August 2007
SC18IM700
V
DD
R PU
Master I
Figure
I
DEVICE
2
C-BUS
R PU
2
12. The SC18IM700 device provides a
C-bus controller with UART interface
I
DEVICE
2
C-BUS
SC18IM700
002aab801
SDA
SCL
© NXP B.V. 2007. All rights reserved.
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