isp1582 NXP Semiconductors, isp1582 Datasheet - Page 32

• Manufacturer Part Number: isp1582
• Description: Hi-speed Universal Serial Bus Peripheral Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ISP1582_6
Product data sheet
8.3.3 Data Port register (address: 20h)
Table 31.
This 2-byte register provides direct access for a microcontroller to the FIFO of the indexed
endpoint. The bit allocation is shown in
Bit
7 to 5
4
3
2
1
0
Symbol
-
CLBUF
VENDP
DSEN
STATUS
STALL
Control Function register: bit description
Description
reserved
Clear Buffer: Logic 1 clears the TX or RX buffer of the indexed endpoint. The
RX buffer is automatically cleared once the endpoint is completely read. This
bit is set only when it is necessary to forcefully clear the buffer. For details,
see
Remark: If using double buffer, to clear both the buffers issue the CLBUF
command two times, that is, set and clear this bit two times.
Validate Endpoint: Logic 1 validates data in the TX FIFO of an IN endpoint to
send on the next IN token. In general, the endpoint is automatically validated
when its FIFO byte count has reached endpoint MaxPacketSize. This bit is set
only when it is necessary to validate the endpoint with the FIFO byte count,
which is below endpoint MaxPacketSize.
Remark: Use either bit VENDP or register Buffer Length to validate endpoint
FIFO with FIFO bytes.
Data Stage Enable: This bit controls the response of the ISP1582 to a control
transfer. After the completion of the set-up stage, firmware must determine
whether a data stage is required. For control OUT, firmware will set this bit
and the ISP1582 goes into the data stage. Otherwise, the ISP1582 will NAK
the data stage transfer. For control IN, firmware will set this bit before writing
data to the TX FIFO and validate the endpoint. If no data stage is required,
firmware can immediately set the STATUS bit after the set-up stage.
Remark: The DSEN bit is cleared once the OUT token is acknowledged by
the device and the IN token is acknowledged by the PC host. This bit cannot
be read back and reading this bit will return logic 0.
Status Acknowledge: Only applicable for control IN or OUT.
This bit controls the generation of ACK or NAK during the status stage of a
SETUP transfer. It is automatically cleared when the status stage is
completed, or when a SETUP token is received. No interrupt signal will be
generated.
0 — Sends NAK
1 — Sends an empty packet following the IN token (peripheral-to-host) or
ACK following the OUT token (host-to-peripheral).
Remark: The STATUS bit is cleared to zero once the zero-length packet is
acknowledged by the device or the PC host.
Remark: Data transfers preceding the status stage must first be fully
completed before the STATUS bit can be set.
Stall Endpoint: Logic 1 stalls the indexed endpoint. This bit is not applicable
for isochronous transfers.
Remark: Stalling a data endpoint will confuse the Data Toggle bit about the
stalled endpoint because the internal logic picks up from where it is stalled.
Therefore, the Data Toggle bit must be reset by disabling and re-enabling the
corresponding endpoint (by setting bit ENABLE to logic 0, followed by logic 1
in the Endpoint Type register) to reset the PID.
Rev. 06 — 20 September 2007
Section
7.9.
Table
32.
Hi-Speed USB Peripheral Controller
© NXP B.V. 2007. All rights reserved.
ISP1582
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